Fractal sequencing schemes for offset cancellation in...

Details Fractal sequencing schemes for offset cancellation in... Fractal sequencing schemes for offset cancellation in...

2005-06-21

2005-06-21

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000, C341S120000

Reexamination Certificate

active

06909388

ABSTRACT:
The present invention is directed to the isolation and cancellation of the offset voltage component typically experienced at the input of sampled-data analog systems. In an exemplary embodiment, offset isolation and cancellation may be performed during normal operation of the sampling circuitry. In an exemplary embodiment, the present invention combines a front-end switching topology with one or more differential integrator stages and a logic algorithm implemented in the differential integrator stages. In operation, the circuitry preferably performs a number of samples for each stage, applies an inversion factor to the samples in accordance with the algorithm and integrates the samples to effect the cancellation of the offset voltage without substantially affecting the sampled input.

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