Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
1998-07-16
2001-02-13
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S211000
Reexamination Certificate
active
06188091
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to a structure and method for designing the wiring layout or routing paths in a programmable logic integrated circuit device for maximizing the number of programmable connections for an available diffusion area or minimizing the diffusion area for a given number of connections.
2. Description of the Prior Art
Field programmable gate arrays (FPGAs) typically have at least two distinct programmable features. One such feature is the logic block, which typically may be programmed to assume a variety of logic functions such as some or all Boolean logic functions for a given number of inputs. The other such feature is the interconnection of such logic blocks via paths that interconnect the outputs and inputs of several logic blocks in a selected sequence to achieve a desired result. Numerous programmable routing structures have been designed to achieve various levels of choice in routing signal paths through a programmable device. U.S. Reissue Pat. No. Re. 34,363, which is incorporated herein by reference and title to which is held by the assignee hereof, discloses a programmable routing structure in the first FPGA.
Such prior art programmable routing structures typically consist of wires programmably connectable by a dispersed number of switching devices such as field effect transistors, the selected conditions of which (i.e., open or closed) determine the chosen path for a signal communicated between programmed logic blocks through such routing structures. Such dispersal of switching devices usually requires numerous diffusion areas within the integrated circuit device, which use a large amount of silicon surface area. To minimize cost, surface area must be used efficiently, particularly where a relatively large number of signal paths must be provided within a relatively small surface area. Therefore, there is a need to use a shared diffusion area which maximizes the number of paths for the diffusion area or, alternatively, minimizes the diffusion area for a given number of paths.
SUMMARY OF THE INVENTION
A structure and method are provided for designing the wiring layout or routing paths in a programmable logic integrated circuit device for maximizing the number of paths for an available diffusion area or, alternatively, for minimizing the required diffusion area for a given number of paths. The structure includes an elongated diffusion area extending along a given direction (the predominant direction) and separated by voltage-controlled transistor gates into serially arrayed adjacent diffusion regions. The method comprises the steps of: selecting four compass directions (wire directions) along the surface of the integrated circuit; selecting a first wire direction, preferably parallel to the predominant direction, for a wire connected to a first diffusion region, preferably located at one end of the diffusion area; selecting the wire direction for a second wire connected to the adjacent diffusion region to be opposite to the first wire direction; proceeding sequentially in the predominant direction along the diffusion area, selecting the third wire direction to be perpendicular to the first wire direction; and selecting the fourth wire direction to be opposite to the direction of the third wire. Thus, the method of the present invention results in the first four wire directions being along the four possible compass directions (i.e., S, N, E, W), with the wires connected to the first two diffusion regions being parallel to each other and the wires connected to the next two diffusion regions being parallel to each other and perpendicular to the first two. The direction of the last wire, connected to the last diffusion region, preferably at the opposite end of the diffusion area from the first diffusion region, may be the same as the direction of the first wire. In the preferred embodiments the last wire is connected to the first wire.
The pattern of four wire directions (for the first “set” of four wires) may be repeated along the entire length of the diffusion area. However, in a first embodiment of the inventive method, the first two wire directions are repeated in each set while the second two wire directions are alternated from set to set.
In a second embodiment, a more extensive pattern is developed. This pattern consists of a sequence wherein the first two wire directions (the first “pair”) from the first set are reversed in the second set, then the second pair are reversed in the third set, the fourth set is a duplicate of the third set, the first pair are reversed again in the fifth set, and the second pair are reversed again in the sixth set.
Additional steps, such as alternating only the second pair along the first half of the diffusion area and then alternating only the first pair along the second half of the diffusion area may also be utilized. The invention also contemplates the step of regularly repeating sequences (patterns) of wire directions along the diffusion area every selected number of wires (preferably a factor of the number of possible directions i.e.,—4).
The single diffusion area of the preferred embodiments can also be divided into multiple smaller diffusion areas wherein the pattern of wires according to the invention is continued from one diffusion area to another. However, the silicon surface area required to implement the routing structure in this fashion will not be minimal, so this approach is not preferred. This approach is also encompassed by the invention.
In addition to assuring single turn connectivity for all of the wires in the routing structure (i.e., every wire can be connected to a wire going in a perpendicular wire direction and another wire going in an opposite wire direction), the present invention also results in a reduction in the number of separate diffusion areas while accommodating all wires and all directions in one elongated, area-limited diffusion area wherein total diffusion area, for a given number of connections, is reduced.
OBJECTS OF THE INVENTION
It is a principal object of the invention to provide a structure and method for laying out wire routing paths for maximum sharing of diffusion area, therefore minimizing diffusion area in a programmable logic integrated circuit device.
It is an additional object of the invention to provide a structure and method for achieving an acceptable wire routing architecture in a programmable logic integrated circuit device which is diffusion area limited.
It is still an additional object of the invention to provide a structure and method for laying out signal routing while making maximum use of available diffusion area on a programmable logic integrated circuit device.
It is still an additional object of the invention to provide an improved programmable logic integrated circuit device having an elongated unitary diffusion area shared by a plurality of routed wires for programmable interconnection thereof wherein the total diffusion area required for such routed wires is minimized by direction selection criteria at junctions along said diffusion area.
REFERENCES:
patent: Re. 34363 (1993-08-01), Freeman
patent: 4484292 (1984-11-01), Hong et al.
patent: 4777606 (1988-10-01), Fournier
patent: 4933738 (1990-06-01), Orbach et al.
patent: 5089973 (1992-02-01), Furtek
patent: 5420447 (1995-05-01), Waggoner
patent: 5481125 (1996-01-01), Harris
patent: 5504439 (1996-04-01), Tavana
patent: 5657242 (1997-08-01), Sekiyama et al.
patent: 5682107 (1997-10-01), Tavana et al.
patent: 5828230 (1998-10-01), Young
patent: 5962881 (1999-10-01), Young
patent: 6020776 (2000-02-01), Young
patent: 6091088 (2000-07-01), Arima et al.
Cartier Lois D.
Hardy David
Xilinx , Inc.
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