FPGA layout for a pair of six input multiplexers

Details FPGA layout for a pair of six input multiplexers FPGA layout for a pair of six input multiplexers

1998-02-13

1999-10-05

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257202, 257203, H01L 2710

Patent

active

059628812

ABSTRACT:
A six-input multiplexer is disclosed using only two transistors in the signal path from an input port to the output port. The multiplexer uses control signals that are not decoded. The multiplexer uses three control signals and requires that the control signal combinations 000 and 111 not be used. The other six control signal combinations 001, 010, 011, 100, 101, and 110 can be used to select between six input signals by placing only two transistors in the signal path, taking advantage of the fact that two of the three control signals are the same and the third is different from the other two. A compact layout results when two multiplexers use common input signals.

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