FPGA integrated circuit having embedded sram memory blocks each

Details FPGA integrated circuit having embedded sram memory blocks each FPGA integrated circuit having embedded sram memory blocks each

1998-12-15

2000-06-27

Le, Vu A.

Static information storage and retrieval

Addressing

365 63, 326 38, 326 41, H03K 19177

Patent

active

06081473&

ABSTRACT:
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals, including a read-mode (RMODE) control signal that switches the memory block between synchronous and asynchronous data transfer modes. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.

REFERENCES:
patent: 5682107 (1997-10-01), Tavana et al
patent: 5838165 (1998-11-01), Chatter

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