FPGA having AC coupling on I/O pins with an effective bypass...

Details FPGA having AC coupling on I/O pins with an effective bypass... FPGA having AC coupling on I/O pins with an effective bypass...

2005-03-10

2008-10-21

Ha, Dac V (Department: 2611)

Pulse or digital communications

Transceivers

C375S257000, C375S316000

Reexamination Certificate

active

07440495

ABSTRACT:
DC balance is obtained in an integrated circuit (IC) having I/O pins with AC coupling by effectively bypassing the AC coupling. The DC balance is accomplished by mixing in a known, low frequency mix signal or carrier in a circuit external to the IC and then digitally canceling out that mix signal inside the IC fabric. The mixer or modulating circuitry external to the IC can be a simple XOR gate. With the IC being an FPGA, the logic internal to the FPGA can be programmed to form the demultiplexing circuitry to digitally cancel out the mix signal, as well as to provide a carrier signal to the external mixer. To minimize errors due to data signal transitions near the edge of the carrier signal, a cleaner circuit is used to eliminate transitioning bits on either side of a carrier signal edge. With modulation used, synchronization circuitry is likewise included to provide synchronization during startup as well as after long dead times in the data signal.

REFERENCES:
patent: 4852123 (1989-07-01), Bickley et al.
patent: 5339040 (1994-08-01), Loper
patent: 6442380 (2002-08-01), Mohindra
patent: 6856788 (2005-02-01), Chang et al.
patent: 7280590 (2007-10-01), Boecker et al.
patent: 2007/0298729 (2007-12-01), Kappes

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