FPGA equivalent input and output grid muxing on structural...

Details FPGA equivalent input and output grid muxing on structural... FPGA equivalent input and output grid muxing on structural...

2006-04-17

2009-06-02

Phung, Anh (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S198000, C365S230020, C710S307000

Reexamination Certificate

active

07542324

ABSTRACT:
The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The memory interface has a first set of lines and a second set of lines. The first and second set of lines are arranged such that there are multiple locations at which a via may be placed to connect a line of the first set to a line of the second set. The placement of the vias determines the bus width of the memory interface.

REFERENCES:
patent: 5867422 (1999-02-01), John
patent: 5870350 (1999-02-01), Bertin et al.
patent: 6242767 (2001-06-01), How et al.
patent: RE38651 (2004-11-01), Sung et al.
patent: 7363422 (2008-04-01), Perego et al.

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