FPGA equivalent input and output grid muxing on structural...

Details FPGA equivalent input and output grid muxing on structural... FPGA equivalent input and output grid muxing on structural...

2011-03-08

2011-03-08

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

C438S128000, C438S622000, C438S637000, C257SE21602, C257SE21613

Reexamination Certificate

active

07901999

ABSTRACT:
The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The memory interface has a first set of lines and a second set of lines. The first and second set of lines are arranged such that there are multiple locations at which a via may be placed to connect a line of the first set to a line of the second set. The placement of the vias determines the bus width of the memory interface.

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