FPGA emulation system

Details FPGA emulation system FPGA emulation system

2011-08-16

2011-08-16

Rodriguez, Paul (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

Reexamination Certificate

active

08000954

ABSTRACT:
This invention features an FPGA emulation system including an FPGA device under test having a plurality of pins. A bus functional model circuit responsive to signals representing predetermined input characteristics of the FPGA device under test and configured to apply one or more signals to the FPGA device under test corresponding to the predetermined input characteristics and configured to receive one or more signals representing output characteristics of the FPGA device under test to emulate the operation of the FPGA device under test in a predefined selectable and flexible electrical operating environment. This invention also features an FPGA emulation system including an FPGA device under test having at least one component and a plurality of pins operating in a predetermined native target environment, a bus functional model engine for simulating and capturing output characteristics of the at least one component of the FPGA device under test and simulating and releasing input characteristics of the at least one component of the FPGA device under test, and a bus functional model circuit embedded in the FPGA device under test configured to receive one or more signals representing the input characteristics of the at least one component and configured to release one or more signals representing the output characteristics of the at least one component such that the bus functional model engine emulates the operation of the at least one component of the FPGA device under test in the predetermined native target environment.

REFERENCES:
patent: 4342093 (1982-07-01), Miyoshi
patent: 4590581 (1986-05-01), Widdoes, Jr.
patent: 4744084 (1988-05-01), Beck et al.
patent: 4769817 (1988-09-01), Krohn et al.
patent: 5036473 (1991-07-01), Butts et al.
patent: 5109353 (1992-04-01), Sample
patent: 5126966 (1992-06-01), Hafeman et al.
patent: 5146460 (1992-09-01), Ackerman et al.
patent: 5479355 (1995-12-01), Hyduke
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5625301 (1997-04-01), Plants et al.
patent: 5682107 (1997-10-01), Tavana et al.
patent: 5809283 (1998-09-01), Vaidyanathan et al.
patent: 5812414 (1998-09-01), Butts et al.
patent: 5958026 (1999-09-01), Goetting et al.
patent: 6020760 (2000-02-01), Sample et al.
patent: 6123735 (2000-09-01), Raghavan et al.
patent: 6286114 (2001-09-01), Veenstra et al.
patent: 6388465 (2002-05-01), Barbier et al.
patent: 6389558 (2002-05-01), Herrmann et al.
patent: 6571204 (2003-05-01), Meyer
patent: 6594802 (2003-07-01), Ricchetti et al.
patent: 6618686 (2003-09-01), Allamsetty
patent: 6650140 (2003-11-01), Lee et al.
patent: 6654919 (2003-11-01), Watkins
patent: 6665855 (2003-12-01), Payne et al.
patent: 6668364 (2003-12-01), McElvain et al.
patent: 6678625 (2004-01-01), Reise et al.
patent: 6678645 (2004-01-01), Rajsuman et al.
patent: 6681353 (2004-01-01), Barrow
patent: 6691266 (2004-02-01), Winegarden et al.
patent: 6754862 (2004-06-01), Hoyer et al.
patent: 6760898 (2004-07-01), Sanchez et al.
patent: 6874107 (2005-03-01), Lesea
patent: 7548841 (2009-06-01), Terashima et al.
patent: 2003/0105617 (2003-06-01), Cadambi et al.
Andrew S. Tanenbaum; Structured Computer Organization, 2nd ed.; 1984; ISBN 0138544239; pp. 10-12.
“Identify Pro”, http://www.synplicity.com/products/identify/index.html Synplicity, Inc., Sunnyvale, CA, Oct. 23, 2008, pp. 1-2.
“ESNUG” (DAC 03, Item 21), Subject: Synplicity Synplify & Identify & Certify, http://www.deepchip.com/items/dac03-21.html, Oct. 23, 2008, pp. 1-8.
“SignalTap II Embedded Logic Analyzer”, Altera Corporation, San Jose, CA, http://www.altera.com//common/print/prt-print.jsp?page=products/2 pages, Jan. 6, 2006, 3 pages.
“Implementing DSP Algorithms in FPGAs”, A detailed overview of Xilinx System Generator for DSP, using a QAM system design example, Xilinx, Inc., San Jose, CA, Oct. 23, 2008, 3 pages.
“Enhanced FPGA Prototyping”, Simpod, Inc., Data Sheet, Santa Clara, CA, 2003, 2 pages.
“SimuTAG links FPGA chips to HDL Simulators”, Product Description, SynaptiCAD, Inc., Blacksburg, VA, Oct. 23, 2008, 3 pages.
Haufe, et al., “Accelerated Logic Simulation by Using Prototype Boards”, Design, Automation and Test in Europe, 1998, Paris, 23.-26.2.98, 183-189.
“ChipScope Pro at a Glance”, ChipScope Pro, Xilinx, Inc., Data Sheet, San Jose, CA, 2005, 3 pages.

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