Fourth-order cascaded sigma-delta modulator

Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder

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375254, H03M 302

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active

054423546

ABSTRACT:
A method of cascading two second-order sigma-delta modulators includes the steps of feeding the input to the quantizer of the first stage to the second stage. This input is, effectively, the difference between the output of the first second-order loop and the quantization noise of the first modulator. The method also includes the step of removing both the quantization noise from the first loop as well as the output from the first loop from a final output, y.sub.out.

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Matsuya, et al., "A 16-Bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping", IEEE Journal of Solid State Circuits, vol. SC-22, No. 6, pp. 921-929, Dec. 1987.
Ribner, et al., "A Third-Order Multistage Sigma-Delta Modulator With Reduced Sensitivity To Nonidealities", IEEE Journal of Solid-State Circuits, vol. 26, No. 12, pp. 1764-1774, Dec. 1991.
Chao, et al., "A Higher Order Topology For Interpolative Modulators For Oversampling A/D Converters", IEEE Transactions on Circuits and Systems, vol. 37, No. 3, pp. 309-318, Mar. 1990.

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