Four-way associative cache with DLAT and separately addressable

Details Four-way associative cache with DLAT and separately addressable Four-way associative cache with DLAT and separately addressable

1989-01-06

1991-10-22

Lee, Thomas C.

Boots, shoes, and leggings

3642434, 36424341, 364253, 3642532, 3642663, 364246, 36424612, 3642463, 364900, 3649621, 3649633, 3649642, 36496434, G06F 1308, G06F 936

Patent

active

050601369

ABSTRACT:
A cache storage system is disclosed which has a high speed buffer (cache), a directory-look-aside-table, and apparatus for maintaining binary coded information signifying the order of use of various sections of the cache. A separately addressable and controllable storage array is provided for each bit position of the binary code so that updating of a code is accomplished by selectively writing certain but not all of the bits in the arrays storing said bits to be updated. This avoids the need to read all bits from an array, change the appropriate bits, then write all bits back into the array. Bits signifying the changed or unchanged state of data in said various sections of the cache are also stored in separately addressable arrays to permit updating of their value merely by selectively writing to the appropriate array.

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