Four transistor cross-coupled bitline content addressable memory

Details Four transistor cross-coupled bitline content addressable memory Four transistor cross-coupled bitline content addressable memory

1987-10-26

1989-05-16

Popek, Joseph A.

Static information storage and retrieval

Associative memories

Ferroelectric cell

365174, G11C 1500

Patent

active

048315850

ABSTRACT:
A content addressable memory cell comprises two storage IGFETs connected between a Match line and respective bitlines. Stored potentials are applied to the gates of the IGFETs through Write IGFETs which are cross coupled to the bitlines. The cross-coupling results in a larger storage capacitance and reduced degenerative capacitive coupling. This improves the speed and noise immunity of the cell. The memory cell is fabricated with three primary levels: a lower level of semiconductor material in which the source, drain and channel of each FET is formed, a center level of conductive material in which the Match and Write lines and the gates of the FETs are formed and an upper level in which the bitlines are formed. The center and lower levels are interconnected at buried contacts.

REFERENCES:
patent: 3701980 (1972-10-01), Mundy
patent: 3969707 (1976-07-01), Lane et al.
patent: 4291391 (1981-09-01), Chatterjee et al.
patent: 4507758 (1985-03-01), Moeschwitzer
patent: 4538243 (1985-08-01), Zehner
patent: 4646271 (1987-02-01), Uchiyama et al.
J. C. Hou, "CAM Cell for Use in Hybrid Memory Scheme", IBM Technical Disclosure Bulletin, vol. 26, No. 8, Jan. 1984, pp. 4331-4334.

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