Four-to-two adder cell for parallel multiplication

Details Four-to-two adder cell for parallel multiplication Four-to-two adder cell for parallel multiplication

1988-09-23

1990-02-13

Harkcom, Gary V.

Boots, shoes, and leggings

364759, G06F 750, G06F 752

Patent

active

049012703

ABSTRACT:
A four-to-two adder for adding four numbers and generating two numbers which has the same sum as the sum of the four input numbers is used to add partial products in a multiplier. A plurality of adder cells are arranged in parallel to process corresponding bits of the four numbers. Each adder cell couples three of the four input bits to the next stage. A four-bit parity circuit is used to control two multiplexers which select signals from a carry generator and the one input signal which is not coupled to the subsequent adder cell stage to provide two output bits corresponding to the two output numbers.

REFERENCES:
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patent: 4270167 (1981-05-01), Koehler et al.
patent: 4338675 (1982-07-01), Palmer et al.
patent: 4484259 (1984-11-01), Palmer et al.
Lai et al., Logic Networks of Carry-Save Adders, IEEE Trans. on Computers, vol. C-31, No. 9, Sep. 1982, pp. 870-882.
Singh et al., Multiple Operand Addition and Multiplication, IEEE Trans. on Computers, vol. C-22, No. 2, Feb. 1973, pp. 113-120.
Shen et al., "4-2 Carry-Save Adder Implementation Using Sand Circuits", IBM Tech. Disclosure Bull., vol. 20, No. 9, Feb. 1978, pp. 3594-3597.
Weinberger, "4-2 Carry-Save Adder Module", IBM Tech. Disclosure Bull., vol. 23, No. 8, Jan. 1981, pp. 3811-3814.
"IEEE Standard for Binary Floating-Point Arithmetic", Std 754-1985 Aug. 12, 1986.
"A Suggestion for a Fast Multiplier"; Wallace; IEEE Transactions on Electronic Computers, Feb. 1964; pp. 14-17.
"Recursive Implementation of Optimal Time VLSI Integer Multipliers"; Luk et al.; BLSI 1983; pp. 155-168.
"Introduction to Arithmetic for Digital Systems Designers"; Waser et al., 1982; Chapter 4.

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