Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent
1984-10-16
1986-07-15
Pellinen, A. D.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
361 91, 361111, 361118, H02H 904
Patent
active
046009604
ABSTRACT:
A solid state electromagnetic pulse suppressor includes first and second external input terminals and first and second external output terminals. The pulse suppressor also includes first and second conductors. The first conductor is electrically connected between the first input terminal and the first output terminal. The second conductor is electrically connected between the second input terminal and the second output terminal. A pulse suppressor element having first and second electrodes has its first electrode attached to an intermediate portion of the first conductor and has its second electrode attached to an intermediate portion of the second conductor. The pulse suppressor element and the portions of the first and second conductors attached thereto are contained in a package. In use, the four terminal pulse suppressor connected in series connection with first and second electrical lines, thereby presenting negligeable inductance between the electrical lines and the pulse suppressor chip and limiting high speed transient voltages across the first and second input terminals.
REFERENCES:
E. Van Keuren, Effects of EMP Induced Transients on Integrated Circuits, IEEE Electromagnetic Compatibility Symposium Record, 75CH1002-5 EMC, 1975.
Owen J. McAteer, Shocking Blow to Military Electronics, Military Electronics/Countermeasures, Jun. 1979.
T. J. Tucker, Spark Initiation Requirements of a Secondary Explosive, Annals of the New York Academy of Sciences, vol. 152, Article I, pp. 643-653, 1968.
O. Melville Clark, Suppression of Fast Rise-Time Transients, Proceedings of 1st Symposium and Technical Exhibition on Electromagnetic Compatibility, IEEE 75CH1012-4 MONT, Montreux, Switzerland, 1975.
General Semiconductor Industries, Inc.
Pellinen A. D.
Wysocki A. Jonathan
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