Four-state switched decoupling capacitor system for active...

Details Four-state switched decoupling capacitor system for active... Four-state switched decoupling capacitor system for active...

2003-01-14

2004-06-01

Vu, Bao Q. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S274000, C323S280000

Reexamination Certificate

active

06744242

ABSTRACT:

BACKGROUND OF THE INVENTION
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to the U.S. patent application entitled “Optimal Inductor Management.” with inventors Robert Paul Masleid, Christoper Giacomotto, and Akihiko Harada and having the same filing date as this application.
1. Field of the Invention
This invention relates to regulating the voltage of an integrated circuit that has an associated package inductance and a variable current demand.
2. Description of Background Art
High-speed microprocessors are increasingly being designed to operate at a low operating voltage and with tight tolerances on acceptable power supply voltage. In particular, individual semiconductor devices and critical logical paths must be able to withstand worst-case voltage variations.
The current demands of a high-speed microprocessor circuit may change rapidly, making it difficult to control the on-chip voltage due to the significant package inductance of a packaged microprocessor circuit. Common package inductance values limit the ability of the package inductor to respond to changes in current demand in time scales less than about 10 nanoseconds. One conventional approach to this problem is to use passive decoupling capacitors to reduce the effect of current changes on microprocessor operating voltage. However, decoupling capacitors require significant die area, particularly if they are to be scaled to permit tight voltage regulation for large, sudden variations in current demand, such as multi-cycle changes in current demand associated with changes in the current required by the microprocessor for multiple clock cycles, such as changes in logic current. Additionally, conventional decoupling capacitors may have difficulty responding to abrupt, multi-cycle changes in current demand.
Therefore what is needed is an improved method of regulating the voltage of a microprocessor associated with changes in current demand of the microprocessor.
SUMMARY OF THE INVENTION
The present invention relates to a voltage regulator for use within an integrated circuit (IC) to regulate multi-cycle voltage fluctuations in the IC having an associated package inductance that limits the rate that current from a regulated voltage source may change in response to a change in current demand of the IC. The voltage regulator sinks current when the operating voltage of the IC rises above a threshold upper trigger voltage indicative of a multicycle decrease in current demand that might lead to an overvoltage condition. The voltage regulator sources current when the operating voltage of the IC decreases below a threshold lower trigger voltage indicative of a multicycle increase in current demand that might lead to an undervoltage condition. In one embodiment, the voltage regulator includes at least two capacitors that are coupled in parallel to sink current, coupled in series to source current, and arc restored to a voltage less than a target operating voltage by a voltage divider to maintain the regulator's ability to sink or source current.


REFERENCES:
patent: 5025203 (1991-06-01), Edwards
patent: 5280233 (1994-01-01), Poletto et al.
patent: 5646572 (1997-07-01), Masleid
patent: 5973547 (1999-10-01), Ang et al.
patent: 6028417 (2000-02-01), Ang et al.
patent: 6069521 (2000-05-01), Taylor et al.
patent: 6198325 (2001-03-01), Ang et al.
patent: 6486718 (2002-11-01), Stelle et al.
U.S. patent application Ser. No. 10/342,588, Masleid, et al., filed Jan. 14, 2003.
Michael Ang, Raoul Salem and Alexander Taylor, WP 26.7 “An On-chip Voltage Regulator Using Switched Decoupling Capacitors”, 2000 IEEE International Solit-State Circuits Conference, Sun Microsystems Inc., Palo Alto, CA, U.S.A.
R. Jacob Baker, Harry W. Li, David E. Boyce, “CMOS Circuit Design, Layout, and Simulation”, 1998, Chapter 24, pp. 579-616, IEEE, Piscataway, NJ, U.S.A.
Ivan Sutherland, Bob Sproull, David Harris, “Logical Effort Designing Fast CMOS Circuits”, 1999, pp. 5-13, Morgan Kaufmann Publishers, Inc., San Francisco, CA, U.S.A.

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