Four rail circuit architecture for ultra-low power and voltage C

Details Four rail circuit architecture for ultra-low power and voltage C Four rail circuit architecture for ultra-low power and voltage C

1996-07-10

1998-09-29

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

257206, H01L 2702

Patent

active

058148450

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention is related to low power consumption circuit architectures and, more specifically, to a circuit architecture for the design of ultra-low power consumption CMOS circuits.
2. Description of the Background of the Invention
Many sophisticated and powerful portable computation and communication devices are currently available. Because such devices are powered by batteries, their endurance between battery charges is limited by the power consumption of the on-board circuits. Thus, power dissipation, rather than the number of transistors or other components, will likely be the key limitation on the signal processing capability of future integrated circuits for portable applications.
The development of economical complimentary metal-oxide semiconductor (CMOS) fabrication techniques was a substantial breakthrough in lowering power requirements. CMOS techniques result in both n-channel and p-channel transistors being fabricated on the same chip. The use of an inverter stage of the type shown in FIG. 1, which is the central idea for other CMOS logic gates, has resulted in some very low-power-drain logic circuitry. As seen in FIG. 1, at any given time, only the upper side (p-channel) or the lower side (n-channel) is on. Thus, there is very little DC current flow from the power source V.sub.CC to ground. The reason there is some current flow is that both transistors are on during a small portion of the input voltage's transitions. Also, stray capacitances are charged from the power supply voltage source and then discharged to ground when the output changes state. Power drain (P.sub.D) can be estimated by using the following relation: (I.sub.1)
As seen from the foregoing equation, when the leakage current is negligible, as is usually the case, the power drain varies as the square of the power supply voltage. Accordingly, reducing the power supply voltage from, for example, 5 volts to 2 volts reduces the power drain as 5.sup.2 to 2.sup.2, or roughly 6 to 1. Thus, voltage scaling has been seriously investigated as a way to reduce power consumption.
For both analog and digital circuits, reducing the power supply voltage is a straight-forward method of decreasing the power requirements. There are, however, several barriers which have prevented the power supply voltages of digital logic circuits from being scaled down to 0.5 volts or lower. For example, there are several fabrication/manufacturing issues that limit how much power supply voltage can be reduced. A primary fabrication/manufacturing issue is that there are substantial variations in the threshold voltage V.sub.T between devices, both systemic variations and random fluctuations. The systemic variations are currently dominant and are contributed to by a large number of factors related to the semiconductor manufacturer's equipment. For a one micron process using six inch (15.24 cm) wafers, one of the primary problems is variation in the poly linewidth defining the effective gate length of the transistors due to variations in the optics across the reticle field. That results in peak-to-peak variations of up to 0.2 volts in the threshold voltage across the reticle. It is expected that the variations in the threshold voltage will be even larger as the gate length decreases to the 0.5 micron level and below.
Additionally, the use of large wafers (e.g. 8 inch (20.32 cm) wafers) results in a further increase in the variations in the threshold voltage due to spacial inhomogeneities in the manufacturing equipment. With a one centimeter by one centimeter die, the systemic variations are smaller, resulting in peak-to-peak variations of roughly 50 millivolts for a one micron process using six inch (15.24 cm) wafers.
There are also variations in threshold voltage from one lot to the next that account for roughly another 0.2 volts of peak-to-peak variation. For example, the MOSIS wafer acceptance range for Orbit p-well and n-well two micron process is greater than 0.5 volts and less than one volt, which is

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