Four quadrant synapse cell employing single column summing line

Details Four quadrant synapse cell employing single column summing line Four quadrant synapse cell employing single column summing line

1990-05-18

1991-07-02

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307464, 307529, 364807, 365185, H03K 1921

Patent

active

050288105

ABSTRACT:
The present invention covers a synapse cell for providing a weighted connection between a differential input voltage and a single output summing line having an associated capacitance. The connection is made using one or more floating-gate transistors which provide both excitatory as well as inhibitory connections. As configured, each transistor's drain is coupled to an input line and its source is coupled to the output summing line. The floating-gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a voltage pulse having a certain duration is applied to the control gate of the floating-gate transistor, a current is generated which acts to discharge the capacitance associated with the output summing line. The current is directly proportional to the charge stored on the floating-gate member and the duration of the input pulse.

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Mackie et al., "Implementations of Neural Network Models in Silicon", NATO Advanced Research Workshop, Neuss, F.R.G., 28 Sep.-2 Oct. 1987.
Hollis et al., "Artificial Neurons Using Analog Multipliers", N. C. State Univ., Manuscript rec'd Dec. 1988.

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