Four quadrant square law analog multiplier using floating gate M

Details Four quadrant square law analog multiplier using floating gate M Four quadrant square law analog multiplier using floating gate M

1996-12-18

1999-01-26

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

327120, 455333, G06F 744

Patent

active

058642552

DESCRIPTION:

BRIEF SUMMARY
I. INTRODUCTION

The present invention relates to the field of analog signal processing and in particular the invention provides a novel four quadrant analog multiplier which makes use of floating-gate MOS technology. The invention also provides an improved programmable synaptic cell employing the four-quadrant analog multiplier of the invention.
It is known in the prior art to construct multiplier circuits using bipolar technology. These prior art devices generally had limited input voltage swing range.
Researchers have also proposed MOS four quadrant analog multipliers based on conventional MOS technology, however these devices are limited in the input signal swing that they will tolerate before significant distortion sets in. Typically these prior art devices cannot accept input levels beyond one half of the supply rail voltage.
Four-quadrant analog multipliers are very useful and important building blocks in many signal processing circuits like correlators, convolvers, adaptive filters, modulation detection, frequency translation, neural networks and etc. So far, several analog multipliers designed in MOS technology based on the modified Gilbert cell (J. N. Babanezhad and G. C. Temes, "A 20-V four-quadrant CMOS analog multiplier," IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1158-1168, December 1985; S. C. Qin and R. L. Geiger, "A .+-.5-V CMOS analog multiplier," IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 1143-1146, December 1987; D. C. Soo and R. G. Meyer, "A four-quadrant NMOS analog multiplier," IEEE J. Solid-State Circuits, vol. SC-17, no. 6, pp. 1174-1178, December 1982), and the square-law characteristic of the MOS have been reported (K. Bult and H. Wallinga, "A CMOS four-quadrant analog multiplier," IEEE J. Solid-State Circuits, vol. SC-21, no. 3 pp. 430-435, June 1986; J. Pena-Finol and J. A. Connelly, "A MOS four-quadrant analog multiplier using the quarter-square technique," IEEE J. Solid-State Circuits. vol. SC-22, no. 6, pp. 1064-1073, December 1973; H. G. Song and C. K. Kim, "A MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers," IEEE J. Solid-State Circuits. vol. 25, no. 3 June 1990; Z. Wang, "A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance," IEEE J. Solid-State Circuits, vol. 26, no. 9, September 1991). The variable transconductance technique based on the Gilbert six transistors cell (GSTC) is very popular and useful in bipolar technology since the output current of a bipolar GSTC has a linear relationship with the tail current source which allows for the nonlinear relationship with the input signals, V.sub.x and V.sub.Y, to be compensated simply by using an appropriate predistortion circuit (P. R. Gray and R. G. Meyer, "Analysis and design of analog integrated circuits, 2nd ed. New York: Wiley, 1984, pp. 593-605). However, the output current of a MOS transistor multiplier based on the GSTC has a nonlinear relationship with tail current source and input signals which makes compensation relatively difficult. By contrast, the square-law based MOS multiplier can be implemented easily because of the inherent square law characteristics of the MOS transistor in the saturation region. PENA-FINOL et.al. have reported a four quadrant analog multiplier based on the quarter-square algebraic identity. Its circuit configuration is relatively complicated and is designed in three stages. In the first stage, the sum and differences of the two input signals are obtained. Then these results are squared in the second stage and the difference of squares is extracted in the third stage. At input signal levels equal to 50% of the supply voltage, 0.73% total harmonic distortion and 0.44% nonlinearity were reported. The multiplier proposed by SONG et.al. is also based on the subtraction of the sum-squared and difference-squared of two input signals. To achieve the squaring of the sum or difference of two inputs, one input is applied to the gate whilst the other one is applied to the sou

REFERENCES:
patent: 3956643 (1976-05-01), Hite
patent: 4751744 (1988-06-01), Pavio, Jr.
patent: 5107150 (1992-04-01), Kimura
patent: 5187682 (1993-02-01), Kimura
patent: 5448197 (1995-09-01), Sagawa et al.
patent: 5559457 (1996-09-01), Uda et al.

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