Four quadrant multiplier circuit and a receiver including such a

Details Four quadrant multiplier circuit and a receiver including such a Four quadrant multiplier circuit and a receiver including such a

1994-02-24

1995-05-09

Pascal, Robert J.

Demodulators

Phase shift keying or quadrature amplitude demodulator

329306, 329327, 327357, H03K 500

Patent

active

054143837

ABSTRACT:
A four quadrant multiplier circuit having a high dynamic range and capable of operating at low voltages includes a dual transconductance amplifier circuit (TAC) consisting of NPN transistors (20 to 23 and 64 to 67), coupled to a first input port (36), first and second folded Darlington circuits (57,58), and a resistive element (78). Each Darlington circuit includes first and second NPN transistors (68,70 and 69,71) whose emitter-collector paths are connected in series and a third PNP transistor (72,73) having its emitter-collector path connected between the collector of the first transistor (68,69) and the base electrode of the second transistor (70,71). The emitter-collector junction (76,77) of the first and second transistors (68,70 and 69,71) is connected to the base electrode of the third transistor (72,73). The resistive element (78) is connected between the base electrodes of the third transistors (72,73). A second input port (56) is connected to the base electrodes of the first transistors (68,69). The emitter currents of the dual transconductance amplifier are supplied by way of current mirror circuits (80,81) from the emitter currents of the second transistors (70,71). The transconductance amplifier circuit (TAC) may be of any suitable type which has its transconductance linearly proportional to its emitter currents. In a refinement of the circuit, the current-to-voltage converter function of the current mirrors is carried out by the second transistors (70,71) and the transistors (82,83) of the current mirror circuits (80,81) are omitted.

REFERENCES:
patent: 3241078 (1966-03-01), Jones
patent: 5115409 (1992-05-01), Stepp
patent: 5311086 (1994-05-01), Yamaji et al.
Chadwick, "Low Power, Low Voltage Receiver Integrated Circuits", Institute of Electronic & Radio Engineers Publ. No. 78, Proc. of the 4th Intn'l Conf., Dec. 15-17, 1987, pp. 155-161.

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