Four-quadrant biCMOS analog multiplier

Details Four-quadrant biCMOS analog multiplier Four-quadrant biCMOS analog multiplier

1995-03-30

1996-12-24

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

327359, 327113, G06G 716, H03K 522

Patent

active

055876820

ABSTRACT:
An analog multiplier circuit includes three transconductance stages. One of the transconductance stages, receiving a first differential voltage, conducts a differential current responsive to the first differential voltage from the other two transconductance stages. The differential current changes the transconductance in the other two transconductance stages, which are cross-coupled with one another. The second differential input voltage is presented to the other two transconductance stages in parallel, resulting in an output differential current or voltage based on the product of the first and second differential input voltages. Each of the transconductance stages is implemented in BiCMOS, and each includes two differential legs, each having a MOS transistor receiving an input signal and a cascode bipolar transistor. Each transconductance stage also includes a reference leg which develops the drain-source voltage for the MOS transistors; the first transconductance stage differentially varies this drain-source voltage in the other two stages to produce the product.

REFERENCES:
patent: 4156283 (1979-05-01), Gilbert
patent: 4546275 (1985-10-01), Penafinol et al.
patent: 4937516 (1990-06-01), Sempel
patent: 5021693 (1991-06-01), Shima
patent: 5107150 (1992-04-01), Kimura
patent: 5151625 (1992-09-01), Zarabadi et al.
patent: 5332937 (1994-07-01), Castello et al.

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