Four quadrant analog multiplier circuit of floating input type

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307498, 328160, G06G 7164

Patent

active

051876825

ABSTRACT:
A four quadrant analog multiplier circuit including first to third squaring circuits 1 to 3 each of which is composed of first and second differential circuits each of which is formed of first and second metal-oxide semiconductor (MOS) transistors M.sub.1 and M.sub.2, M.sub.3 and M.sub.4, M.sub.5 and M.sub.6, M.sub.7 and M.sub.8, M.sub.9 and M.sub.10, and M.sub.11 and M.sub.12. A gate width-to-length ratio W.sub.2 /L.sub.2 of the second MOS transistor M.sub.2 is larger than a gate width-to-length ratio W.sub.1 /L.sub.1 of the first MOS transistor M.sub.1. A gate of the first MOS transistor M.sub.1, M.sub.5 and M.sub.9 of each first differential circuit is connected to a gate of the second MOS transistor M.sub.4, M.sub.8 and M.sub.12 of the corresponding second differential circuit. A gate of the second MOS transistor M.sub.2, M.sub.6 and M.sub.10 of each first differential circuit is connected to a gate of the first MOS transistor M.sub.3, M.sub.7 and M.sub.11 of the corresponding second differential circuit. The gates of the MOS transistors M.sub.1 and M.sub.9 are connected in common to receive a first input signal V.sub.1, and the gates of the MOS transistors M.sub.5 and M.sub.11 are connected in common to receive a second input signal V.sub.1. Drains of the MOS transistors M.sub.1, M.sub.3, M.sub.5, M.sub.7, M.sub.10, and M.sub.12 are connected in common to a first output current terminal, and drains of the MOS transistors M.sub.2, M.sub.4, M.sub.6, M.sub.8, M.sub.9, and M.sub.11 are connected in common to a second output current terminal. A differential current between the first and second output current terminals is indicative of a product of the input signals V.sub.1 and V.sub.2.

REFERENCES:
patent: 3689752 (1972-09-01), Gilbert
patent: 3838262 (1974-09-01), Van de Plassche
patent: 4978873 (1990-12-01), Shoemaker
patent: 5115409 (1992-05-01), Stepp

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