Four quadrant analog mixer-based delay-locked loop for clock...

Details Four quadrant analog mixer-based delay-locked loop for clock... Four quadrant analog mixer-based delay-locked loop for clock...

2001-09-06

2003-07-01

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S235000

Reexamination Certificate

active

06586977

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to clock and data recovery circuits and, more specifically, to a four quadrant analog mixer-based delay-locked loop (DLL) for clock and data recovery.
BACKGROUND OF THE INVENTION
The exponential growth of high speed digital communication systems creates a tremendous demand for high speed chip-to-chip interconnect systems over short printed circuit board (PCB) traces or across a backplane. In such communication systems, data is transmitted without a separate clock signal and is typically referred to as asynchronous communication. Since a separate clock signal is not used, at a receiver side of a communications system, a so-called “clock recovery circuit” is employed to extract clock information from incoming data signals. Once extracted, the recovered clock is then used to re-time and regenerate the data originally transmitted. This clock and data recovery circuit (CDR) may be constructed with a phase-locked loop (PLL) or a delay-locked loop (DLL) circuit within the CDR.
A DLL performs a phase shift of a phase delay of an input clock signal and aligns the phase of the delayed clock to a reference signal. A voltage control delay element is employed in a DLL circuit to achieve the delay. One specific technique to realize this voltage control delay element is to use an analog quadrature mixer. Provided there are local in-phase and quadrature phase clock signals (usually denoted as I and Q, respectively), by multiplying the I and Q signals with first and second voltage control signals (for example, V
A
and V
B
) and then adding the products together, an output signal S
out
may be expressed in the following equation.
S
out
=(
V
A
·I
)+(
V
B
·Q
)
In this example, the phase of the output signal S
out
is directly controlled by the voltage control signals V
A
, V
B
. More specifically, if the first voltage control signal V
A
is decreasing and the second voltage control signal V
B
is increasing, the output signal S
out
, represented as a vector, is moving towards the in-phase clock signal I. In addition, if the first voltage control signal V
A
is increasing and the second voltage control signal V
B
is decreasing, the output signal S
out
vector is moving towards the quadrature phase clock signal Q. This particular DLL technique has been employed in numerous conventional CDR systems.
Unfortunately, in such prior art systems, the phase interpolation to derive the output signal vector S
out
is only performed in the first quadrant, where the voltage control signals V
A
, V
B
are both positive. Thus, in order to extend the phase interpolation to the other quadrants, switching between I and I
B
, and Q and Q
B
, is required, where I
B
and Q
B
are represented by signals 180 degrees out of phase with the in-phase and quadrature phase signals I, Q, respectively. Although successful in extending the phase interpolation of an output signal S
out
to the other quadrants, the switching operation introduces phase discontinuity at the quadrant borders, which typically results in large jitter in the CDR, as well as “phase jump” at the borders. Employing a PLL-based circuit to provide phase interpolation of the output signal Sout in all quadrants is also possible, however the large power consumption typical of PLL-based CDRs leads designers to lean towards DLL circuits. In addition, PLL circuits also often introduce excessive jitter to a CDR, primarily due to discrete phase selection steps characterized by this type of architecture, thus resulting in a phase interpolation that is not truly continuous.
Accordingly, what is needed in the art is DLL circuitry for clock and data recovery that does not suffer from the deficiencies found in the prior art.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides DLL circuits and method of recovering a clock signal and data. One DLL includes: (1) a phase detector that generates a phase difference signal based on a phase comparison between a data signal and a mixer output signal of the DLL and (2) a quadrant controller, coupled to the phase detector, that generates first and second control signals based on the phase difference signal and first and second voltage control signals of the DLL.
In another aspect, the present invention provides a method of performing clock and data recovery. In one embodiment, the method includes generating a phase difference signal based on a phase comparison between a data signal and a mixer output signal of the DLL, and generating first and second voltage control signals based on the phase difference signal and first and second voltage control signals of the DLL.
In yet another aspect, the present invention provides a four quadrant DLL circuit. This DLL includes a phase detector that generates a phase difference signal based on a phase comparison between a data signal and a mixer output signal of the DLL, and a quadrant controller, coupled to the phase detector, that generates first and second voltage control signals based on the phase difference signal and first and second voltage control signals of the DLL. The DLL further includes an amplitude controller, coupled to the quadrant controller, that generates in-phase and quadrature phase control signals based on the first and second voltage control signals and the first and second voltage control signals. Also included are in-phase and quadrature phase charge pump circuits, coupled to the amplitude controller, that generate the first and second voltage control signals based on the in-phase and quadrature phase control signals. The DLL still further includes a mixer coupled to the in-phase and quadrature phase charge pump circuits.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.


REFERENCES:
patent: 6078200 (2000-06-01), Miyano
patent: 6115586 (2000-09-01), Bezzam et al.
patent: 6194929 (2001-02-01), Drost et al.

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