Four memory state EEPROM

Details Four memory state EEPROM Four memory state EEPROM

1991-05-07

1992-10-27

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365182, G11C 1300

Patent

active

051595702

ABSTRACT:
An EEPROM memory cell having sidewall floating gates (28, 28a, 28b) is disclosed. Sidewall floating gates (28, 28a, 28b) are formed on sidewalls (30, 32) of a central block (22). Spaced apart bit lines (36, 36a, 36b) are formed to serve as memory cell sources and drains. Sidewall floating gates (28a, 28b) are capable of being programmed independently of one another. When control gate (18) is actuated and either bit line (36a) or bit line (36b) is used to read the device, four separate memory states may be identified depending on whether either, neither or both of the sidewall floating gates (28a, 28b) have been programmed.

REFERENCES:
patent: 4811067 (1989-03-01), Fitzgerald et al.
patent: 4907047 (1990-03-01), Kato et al.

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