Four-gate transistor analog multiplier circuit

Details Four-gate transistor analog multiplier circuit Four-gate transistor analog multiplier circuit

2011-08-30

2011-08-30

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical analog calculating computer

Particular function performed

Reexamination Certificate

active

08010591

ABSTRACT:
A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

REFERENCES:
patent: 5523717 (1996-06-01), Kimura
patent: 5581210 (1996-12-01), Kimura
patent: 5712810 (1998-01-01), Kimura
Akarvardar et al, “A Novel Four-Qadrant Analog Multiplier Using SOI Four-Gate Transistors (G-FETs)”, Pasadena, CA: Jet Propulsion Laboratory, National Aeronautics and Space Administration, Sep. 2005.
Akarvardar, Kerem, et al., “Depletion-All-Around Operation of the SOI Four-Gate Transistor”,IEEE Transactions on Electron Devices, vol. 54, No. 2, (323-331), (Jan. 2007), 9.
Cristoloveanu, Sorin, et al., “A Review of the SOI Four-Gate Transistor”,IEEE, (2006), 4.

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