Four F-squared gapless dual layer bitline DRAM array...

Details Four F-squared gapless dual layer bitline DRAM array... Four F-squared gapless dual layer bitline DRAM array...

1999-09-29

2001-08-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S069000, C257S776000, C257S907000

Reexamination Certificate

active

06282113

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the field of semiconductor memory devices, and in particular to a DRAM array having a compact folded bitline architecture.
It is a continuing goal in computer memory design, such as in the design of Dynamic Random Access Memory (DRAM) arrays, to achieve increased storage capacity in smaller devices. Typically, this entails finding ways of packing memory cells as densely as possible into as small an area as possible.
In DRAM arrays, individual memory cells are accessed by bitlines and wordlines. Generally speaking, one limitation on the degree to which the size of a memory cell in an array can be reduced is determined by the “pitch” of the bitlines and wordlines required to address a single cell. A pitch is equivalent to the width of a bitline or wordline, plus the distance to neighboring bitlines or wordlines in the array.
FIG. 9A
shows a memory cell
900
in a DRAM array. The cell is accessed, for reading from or writing to, by a bitline
901
and a wordline
902
.
FIG. 9A
illustrates, for example, that for a bitline pitch of 3F (where “F” is the minimum lithographic feature size and is technology-dependent) and a wordline pitch of 2F, the minimum size for a memory cell in the array is approximately 6F
2
. Similarly, as shown in
FIG. 9B
, for a bitline pitch of 2F and a wordline pitch of 2F, a memory cell
903
having an area of only 4F
2
can be accessed.
Folded bitline architecture is known in DRAM arrays. In folded bitline architecture, the voltage on a selected bitline is compared to a voltage on a complement bitline. The complement bitline provides a reference signal for comparison to the signal on the selected bitline such that the actual stored bit in an array memory cell is distinguished as the difference between signals on the selected bitline and the complement bitline.
Conventionally, in a folded bitline DRAM, the bitlines of the memory array are laid out so that each bitline and its associated complement are parallel to each other on the same level.
FIG. 9C
shows an example of a memory cell accessed by a folded bitline architecture. In
FIG. 9C
, bitline
901
and its complement {overscore (
901
)}, and wordline
902
are used to access memory cell
904
. The arrangement requires a minimum of about 8F
2
semiconductor area per cell to implement.
Open bitline architectures are known which have a theoretical minimum of 4F
2
array area per cell, but folded bitline architecture is preferable in that it provides better noise immunity.
Techniques have been disclosed for providing the advantages of folded bitline architecture while reducing the minimum cell area required. Nakano et. al (1996 Symposium on VLSI Circuits Digest of Technical Papers, p. 190-191) describes a bitline architecture in which a bitline and its complement are vertically parallel on subsequent levels rather than being adjacent and parallel on the same level. The lower bitline is connected to the underlying cells by contacts. The bitline and its complement exchange levels in “twist regions” at one or more locations in order to match capacitance. The architecture supports a minimum cell size of 5-6F
2
.
However, the twist region layout of Nakano et al. does not allow the array to continue uninterrupted through the twist region. Instead, a gap, i.e., an absence of memory cells, in the layout pattern exists which reduces the array density. The gap is necessitated by a crowding of contacts within the twist region, and by a third metal level which is used for the exchange of bitline levels. As this level is normally fully utilized within the array as the wordline, a gap in the array is required to allow its use within the twist region.
U.S. Pat. No. 5,821,592 to Hoenigschmid et al. describes a bitline architecture which eliminates the afore-mentioned gaps, to achieve an improvement in array density. The architecture supports a minimum cell size of approximately 6F
2
.
SUMMARY OF THE INVENTION
A semiconductor device according to the present invention achieves a folded bitline architecture for a DRAM array with minimum cell area requirements comparable to those of open bitline architectures, while eliminating gaps in the array. According to the present invention, a bitline and its complement are stacked adjacently in lower and upper levels over a memory cell array, rather than being adjacent and parallel on the same level. The bitline and its complement alternate between the upper and lower levels.
In such a bitline pair, the lower bitline is connected to the memory cells and is interrupted by breakpoints with a predetermined spacing. In selected intervals between the breakpoints, the upper bitline is positioned at a predetermined angle relative to the lower bitline, and connects with the lower bitline at the breakpoints to effect the exchange of levels.
In a plurality of such bitline pairs in the architecture, a displacement between breakpoints in adjacent lower bitlines is determined so as to effect a staggering of breakpoints whereby a plurality of diagonal “twist regions” are defined, each twist region including breakpoints in alternating lower bitlines.
The diagonal structure of the layout associated with the staggering of breakpoints, and the angling of the upper bitlines with respect to the lower bitlines allow the underlying cell array to continue without interruption, while maintaining a lower bitline pitch of approximately 2F. Thus, the twist region gap of the prior art is avoided, while enabling support for a minimum cell area of approximately 4F
2
.


REFERENCES:
patent: 4402063 (1983-08-01), Wittwer
patent: 5107459 (1992-04-01), Chu et al.
patent: 5194752 (1993-03-01), Kumagai et al.
patent: 5315542 (1994-05-01), Melzner
patent: 5416734 (1995-05-01), Hidaka et al.
patent: 5821592 (1998-11-01), Hoenigschmid et al.
patent: 5864496 (1999-01-01), Mueller et al.
patent: 6108230 (2000-08-01), Anh et al.
Nakano, H., et al., “A dual layer bitline DRAM array with Vcc/Vss/Vss hybrid precharge for multi-gigabit DRAMs,” 1996 Symp. on VLSI Circuits Digest of Technical Papers, pp. 190-191.

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