Four clock phase N-channel MOS gate

Details Four clock phase N-channel MOS gate Four clock phase N-channel MOS gate

1978-12-07

1981-03-17

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307270, 307DIG4, H03K 17687, H03K 1726, H03K 1728

Patent

active

042569761

ABSTRACT:
In an N-channel MOS integrated circuit operating in response to a major-major clock having four phases, .phi.1, .phi.2, .phi.3 and .phi.4, each of which has one, but only one, other phase which does not overlap therewith, an improved gate is disclosed wherein a first one of said phases samples an input signal for retention via a capacitive device, a second one of said phases is gated according to the state of the sample retained via the capacitive device, and a third one of said phases enhances the retention of the capacitive device.

REFERENCES:
patent: 3699539 (1972-10-01), Spence
patent: 3794856 (1974-02-01), Baker
patent: 3835457 (1974-09-01), Yu
patent: 3898479 (1975-08-01), Proebsting
patent: 4081699 (1978-03-01), Hirt et al.
patent: 4084106 (1978-04-01), Ullrich
Chu et al., "Bootstrap Push-Pull Driver"; IBM Tech. Discl. Bull.; vol. 18, No. 3, pp. 710-711; 8/1975.

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