Four bit pre-fetch sDRAM column select architecture

Details Four bit pre-fetch sDRAM column select architecture Four bit pre-fetch sDRAM column select architecture

1996-09-23

1998-09-01

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

365 51, 365 63, G11C 800

Patent

active

058020055

ABSTRACT:
A synchronous DRAM memory device has four banks B0, B1, B2 and B3 of memory cell arrays 302-332 arranged across the length of the substrate 300. Each received address causes column address generators to select four bits of data for each bit of data in a data word. Data sequence circuits convey the four selected data bits to data bit bond pads 334,336 on the substrate in timed and selected sequential or interleaved order.

REFERENCES:
patent: 5517442 (1996-05-01), Kirihata et al.
patent: 5596541 (1997-01-01), Toda
Copy of Foils Presented at JEDEC Meeting Mar. 15, 1995 by Masayuki Nakamura .

Affiliated with

Also associated with

Rating

Four bit pre-fetch sDRAM column select architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Four bit pre-fetch sDRAM column select architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Four bit pre-fetch sDRAM column select architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-277095