Four-bit non-volatile memory transistor and array

Details Four-bit non-volatile memory transistor and array Four-bit non-volatile memory transistor and array

2006-03-21

2006-03-21

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185010, C365S185180, C365S185240, C365S185260, C365S185270

Reexamination Certificate

active

07016225

ABSTRACT:
A non-volatile memory cell capable of storing more than two bits of information. The NVM cell includes a semiconductor region having a first conductivity type, and a plurality of field isolation regions located in the semiconductor region. Four or more source/drain regions are located in the semiconductor region adjacent to the field isolation regions, the source/drain regions having a second conductivity type, opposite the first conductivity type. The field isolation regions and the source drain regions laterally surround a channel region in the semiconductor region. A gate structure, including a floating gate structure and a control gate structure, extends over the channel region, portions of the field isolation regions and portions of the source/drain regions. The floating gate structure includes a plurality of charge trapping regions, wherein each of the charge trapping regions is located adjacent to a corresponding one of the source/drain regions.

REFERENCES:
patent: 6044022 (2000-03-01), Nachumovsky
patent: 6456531 (2002-09-01), Wang et al.
patent: 6552387 (2003-04-01), Eitan

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