Four-bit block write for a wide input/output random access memor

Details Four-bit block write for a wide input/output random access memor Four-bit block write for a wide input/output random access memor

1994-03-11

1999-11-23

Zarabian, A.

Static information storage and retrieval

Plural shift register memory devices

36523003, G11C 1900

Patent

active

059911867

ABSTRACT:
A data processing system includes a data processor and a random access memory arranged with plural memory planes. Each memory plane includes N memory arrays; N serial registers, each serial register coupled to a memory array; N block write control circuits; a row address decoder; and a column address decoder arranged for both block decoding and individual column decoding. An address bus and a data bus connect the data processor with all of the memory arrays. Random access for writing data into the N memory arrays may be by individual bits or by blocks of bits. The plural memory planes, the address bus, and the data bus are all fabricated on a single semiconductor substrate. A Z-buffer memory with plural Z-buffer planes may also be included. Each Z-buffer plane includes N Z-buffer arrays; N Z-buffer block write control circuits; a Z-buffer row address decoder; and a Z-buffer column address decoder arranged for both block decoding and individual column decoding. The address bus and the data bus further connect the data processor with all of the Z-buffer arrays for random access writing of data by individual bits or by blocks of bits to the Z-buffer memory.

REFERENCES:
patent: 4747081 (1988-05-01), Heilveil
patent: 4807189 (1989-02-01), Pinkham
patent: 5381376 (1995-01-01), Kim

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