Electric power conversion systems – Current conversion – Using semiconductor-type converter
Reexamination Certificate
2000-11-03
2002-04-09
Patel, Rajnikant B. (Department: 2838)
Electric power conversion systems
Current conversion
Using semiconductor-type converter
C363S017000, C363S040000
Reexamination Certificate
active
06370051
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to DC-to-DC power converter circuits, and more particularly, to a two-switch forward converter circuit that provides substantially reduced switching losses by setting the voltage across the main switches to zero prior to their respective conduction states.
2. Description of Related Art
Two-switch forward converter circuits are known in the art for providing a relatively high DC voltage pulse modulated source on a primary side of a transformer of a DC-to-DC power converter circuit. An example of a conventional two-switch forward converter circuit is provided in FIG.
1
. The two-switch forward converter circuit derives its name from two MOSFET switches
12
,
14
that are used to periodically switch the bus voltage (V
BUS
) across the primary side of a transformer
20
. The bus voltage (V
BUS
) is typically a relatively high DC level, such as 380 volts.
As shown in
FIG. 1
, the first switch
12
has a drain terminal coupled to V
BUS
and a source terminal coupled to a first end (A) of the primary winding of the transformer
20
. The second switch
14
has a source terminal coupled to ground and a drain terminal coupled to a second end (B) of the primary winding of the transformer
20
. The first end (A) of the transformer
20
is coupled to ground through a diode
16
and the second end (B) of the transformer is coupled to V
BUS
through a diode
18
. The gate terminals of the first and second switches
12
,
14
are driven by a pulse width modulator input signal (PWM IN). The gate terminal of the first switch
12
is driven through a drive transformer
22
in order to float the source voltage with respect to ground. The gate terminal of the second switch
18
is driven directly by PWM IN. It should be appreciated that each of the switches
12
,
14
includes an internal body diode and a body capacitor (C
DS
) defined between drain and source terminals thereof.
The operation of the two-switch forward converter circuit of
FIG. 1
is illustrated with respect to the timing diagrams of FIG.
2
. In
FIG. 2
, the PWM IN signal is illustrated as a series of rectangular pulses having a predetermined duty cycle. In the time prior to issuance of a first pulse, the forward converter circuit is in a steady-state condition in which both switches
12
,
14
are off (i.e., non-conducting). The voltages at end A of the transformer (V
A
) and at end B of the transformer (V
B
) have equalized at roughly half of the bus voltage (V
BUS
), so the voltage across the transformer (V
A-B
) is zero. The body capacitors C
DS
of each of the switches
12
,
14
are charged. When the PWM IN signal goes from low to high, both switches
12
,
14
are turned on, causing V
A
to rise to V
BUS
and V
B
to fall to ground so that the full bus voltage V
BUS
is across the transformer
20
. This causes current to flow through both switches
12
,
14
and through the primary winding of the transformer
20
to deliver power to the secondary winding of the transformer. In this state, the voltage across the transformer
20
is the bus voltage V
BUS
.
When the PWM IN signal goes from high to low, both switches
12
,
14
are turned off. The leakage and magnetization current in the transformer
20
starts to charge the body capacitors C
DS
of each of the switches
12
,
14
. This causes V
A
to fall to ground and V
B
to rise to V
BUS
so that the negative bus voltage −V
BUS
is across the transformer
20
. When the voltage across the switches
12
,
14
reaches V
BUS
, magnetization current starts to flow through the diodes
16
,
18
, and the transformer
20
starts resetting by dumping magnetization energy back to the bus. After a period of time, the transformer
20
has zero magnetization current and the current through the diodes
16
,
18
drops to zero, and the forward converter circuit returns to the steady-state condition described above. Some ringing generally occurs as the voltage across the transformer
20
returns to zero, as depicted in FIG.
2
.
A significant drawback of the two-switch forward converter circuit is that it is inefficient for three reasons. First, the stored charge in the body capacitors C
DS
of each of the switches
12
,
14
is lost when the switches are turned on. Even if the switches were turned on with zero current, there is loss of efficiency due to the discharge of the body capacitors C
DS
. Second, the switches
12
,
14
have transition power loss when they change state since there is voltage between the drain and source terminals and current flowing between the drain and source terminals during the transition period. The transition current and voltage causes a power surge in the device. Third, there is resistive loss of the switches
12
,
14
due to the drain-to-source resistance (R
DS
) of the MOSFETs. While this third inefficiency can be minimized by selecting MOSFETs having low drain-to-source resistance R
DS
, it cannot be entirely eliminated. If the switches
12
,
14
could be adapted to change state with zero voltage and zero current, a substantial improvement in efficiency of the two-switch forward converter circuit could be attained.
Accordingly, it would be desirable to provide a two-switch forward converter circuit having substantially reduced switching losses to provide greater efficiency than the aforementioned conventional circuit. More specifically, it would be desirable to provide a two-switch forward converter circuit having switches that change state with substantially zero voltage and zero current.
SUMMARY OF THE INVENTION
The present invention is directed to a forward converter circuit having substantially reduced switching losses to provide greater efficiency than the aforementioned conventional circuit. The forward converter circuit is similar to the conventional circuit in that it includes a transformer having primary and secondary windings, and two switches used to couple the primary windings to bus voltage and ground, respectively. Unlike the conventional circuit, however, the present invention further includes a third switch adapted to increase the rate of removal of magnetization current from the transformer in between operational cycles so as to reduce the switching losses of the two primary switches.
In an embodiment of the invention, a first switch is coupled to a primary winding of a transformer and adapted to selectively couple a bus voltage terminal to a first terminal of the primary winding. A second switch is coupled to the transformer and adapted to selectively couple a second terminal of the primary winding to ground. The first and second switches are triggered in response to a first periodic gate control signal. A diode is coupled between the bus voltage terminal and the second terminal of the primary winding of the transformer. A third switch is coupled to the transformer and adapted to selectively couple the first terminal of the primary winding of the transformer to ground. The third switch is triggered in response to a second periodic gate control signal. The second periodic gate control signal is substantially inverted with respect to the first periodic gate control signal. A capacitor is coupled in parallel with the second switch. Power from the bus voltage terminal is transferred from the primary winding to the secondary winding of the transformer during a portion of an operational cycle of the forward converter circuit with the first and second switches being in a conductive state responsive to the first periodic gate control signal.
More specifically, the first periodic gate control signal further comprises a rectangular waveform having a predetermined duty cycle. The second periodic gate control signal further comprising a rectangular waveform having an inverted duty cycle with respect to the predetermined duty cycle of the first periodic gate control signal. A first time delay period is defined between a trailing edge of the second periodic gate control signal and a leading edge of the first periodic gate control signal. A second time del
O'Melveny & Myers LLP
Patel Rajnikant B.
Power-One, Inc.
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