Forward-backward channel interpolator

Pulse or digital communications – Equalizers – Automatic

Reexamination Certificate

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C708S704000

Reexamination Certificate

active

06173011

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to digital communication systems and, more particularly, to interpolators for use in digital communication systems.
BACKGROUND INFORMATION
Some digital communication systems use equalization to increase accurate detection of transmitted symbols in the presence of intersymbol interference (ISI). Equalization can be used to compensate for this ISI so that the transmitted symbols are accurately detected. Such equalization systems are well known (see for example, U.S. Pat. Nos. 5,414,734 and 5,513,15 for a discussion of equalization).
FIG. 1
is a simplified diagram illustrative of a system
10
that uses equalization.
System
10
includes a transmitter
12
, a receiver
14
with an equalizer
16
. In this example, system
10
is a mobile wireless digital system in which transmitter
12
broadcasts radiofrequency (RF) signals that are modulated to include digital information. In this system, transmitter
12
receives symbols x(t), which transmitter
12
modulates and broadcasts. Each symbol generally represents one or more bits. For example, each symbol of a sixteen-level quadrature amplitude modulation (QAM) scheme represents four bits.
The broadcasted symbol is propagated through a channel
18
, which is indicated by a dashed box in FIG.
1
. Receiver
14
then receives the broadcasted symbol. Although omitted from
FIG. 1
for clarity, in system
10
receiver
14
generally receives a transmission through more than one transmission path. For example, the multiple paths may be the result of more than one transmitter being used to transmit the signals and/or the transmitted signal from a single transmitter being reflected from nearby structures. Typically, the transmission paths between receiver
14
and the various other transmitters are not equal in length and may be changing over time (due to receiver
14
being moved while receiving a symbol), thereby resulting in multipath fading and ISI. Channel
18
represents the multiple paths and can include effects from the transmitter and receiver (e.g., pulse shaping filters, modulation inaccuracies, etc.). Typically, channel
18
is modeled as a time-variant finite impulse response (FIR) filter.
Equalizer
16
compensates for ISI as the ISI changes over time. This compensation allows receiver
14
to more accurately detect the received symbols. The compensation provided by equalizer
16
can be adjusted during operation based on periodically generated estimates of the channel response where the channel is modeled as in system
10
.
FIG. 2
is a simplified functional block diagram illustrative of conventional exemplary equalizer
16
(FIG.
1
). Equalizer
16
includes a decision feedback equalizer circuit (DFE)
22
, a channel estimator
24
and a channel interpolator
26
. For example, U.S. Pat. No. 5,513,215 discloses an estimator with a DFE, channel estimator and channel interpolator. The basic operation of exemplary equalizer
16
is as follows. Symbol samples are received by receiver
14
(
FIG. 1
) and propagated to DFE
22
and channel estimator
24
. Channel estimator
24
and channel interpolator
26
operate to periodically provide, in effect, a highly “defined” estimate of the response of channel
18
. This interpolated estimate of the channel response allows computation of the coefficients of DFE
22
so that DFE
22
can accurately detect the received symbols.
More specifically, channel estimator
24
uses known pilot symbols that are periodically inserted in the transmitted data sequence. The rate at which the pilot symbols are inserted is related to the highest fading rate that channel estimator
24
can follow. In particular, the frequency of the pilot symbol injection is about two or more times the fading rate that the channel estimator
24
can track (i.e., meeting Nyquist rate constraints). For example, a paging system application adapted for use in a fading environment with a fading rate of about 100 Hz, the pilot symbol insertion rate may be set at about 360 Hz.
Channel interpolator
26
uses the channel estimates from channel estimator
24
to compute the interpolated channel estimates to match the frequency of the received symbols transmitted by transmitter
12
(FIG.
1
), or with a higher frequency than the symbol frequency if the receiver uses oversampling techniques. In the aforementioned paging system application, the symbol rate may be about 18 kHz. Thus, the 360 Hz pilot symbol insertion rate requires that channel interpolator
26
interpolate the channel estimates on the order of fifty times. In such cases, high-order interpolators (i.e., fifty or greater) are typically implemented with multistage interpolators to reduce computational load.
FIG. 3
is a block diagram illustrative of multistage channel interpolator
26
(FIG.
2
). To get any order of interpolation and a linear phase response of the interpolator, channel interpolator
26
is conventionally implemented using a zero-stuffing technique with filtering through several FIR filter stages
31
1
-
31
j
and applying a linear interpolator
53
at the end as a last stage. Linear interpolator
53
is able to implement even the noninteger interpolation values. It can be used as the final stage of interpolation because the earlier FIR filter stages
31
1
-
31
j
interpolate the estimated impulse response to well above the Nyquist rate of channel estimator
24
, which is determined by the pilot symbol insertion rate. In addition, because the channel fading process is sampled so that the Nyquist rate is close to the fading rate, the first FIR filter stage
31
1
generally must have a relatively narrow transition bandwidth to filter out noise and prevent aliasing. However, to achieve a narrow transition bandwidth in an FIR filter, a relatively large number of coefficients is required. The large number of coefficients undesirably incurs a relatively large computational load and a relatively large initial filter delay. Accordingly, there is a need for a channel interpolator that has a first stage that provides a narrow transition bandwidth with a linear phase response with fewer filter coefficients.
SUMMARY
In accordance with the present invention, a multistage interpolator is provided having a linear phase response and a first stage with a narrow transition bandwidth. Interpolation is achieved by upsampling the sequence to be interpolated using zero-stuffing techniques and then digitally filtering the sequence. In one aspect of the invention, the first stage is implemented with an infinite impulse response (IIR) filter to achieve the narrow transition bandwidth with relatively few filter coefficients. The smaller IIR filter tends to reduce both the computational load required for the filtering and the guard blocks to avoid the effects of the filter transients.
In another aspect of the present invention, a forward-backward filtering methodology is used to achieve a linear phase response for the IIR filter. In particular, the input sequence to be interpolated is stuffed with zeros according to the order of the interpolation and passed through the IIR filter a first time. Then the time order of the resulting sequence is reversed and then passed through the IIR filter a second time. Finally, the resulting output sequence is reversed again. As a result, the forward-backward filtering achieves a linear phase response.
In yet another aspect of the present invention, a block of zeros is appended to the input sequence so that the startup and ending transient effects of the IIR filter's step response are equal at both ends, which tends to improve the accuracy of the interpolation.


REFERENCES:
patent: 5263053 (1993-11-01), Wan et al.
patent: 5337264 (1994-08-01), Levien
patent: 5479922 (1996-01-01), Reichl
patent: 5513215 (1996-04-01), Marchetto et al.
patent: 5553013 (1996-09-01), Davis, Jr. et al.
patent: 5592517 (1997-01-01), Camp et al.
patent: 5627859 (1997-05-01), Parr
patent: 5703887 (1997-12-01), Heegard et al.
patent: 5774564 (1998-06-01), Eguchi et al.
patent: 5777908 (1998-07-01), Inogai
patent

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