Forming wide dielectric-filled planarized isolation trenches in

Details Forming wide dielectric-filled planarized isolation trenches in Forming wide dielectric-filled planarized isolation trenches in

1989-10-25

1991-04-09

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437203, 437228, H01L 2182

Patent

active

050064827

ABSTRACT:
A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si.sub.3 N.sub.4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si.sub.3 N.sub.4 into the substrate by conventional RIE. The surface of the substrate including the trenches have formed thereon a SiO.sub.2 coating, conforming to the surface of the substrater. A layer of etch resistant material such as polysilicon is deposited onto the SiO.sub.2 material. The polysilicon outside the width of the trenches is then removed by chemical-mechanical polishing to expose the SiO.sub.2 there below, while leaving the SiO.sub.2 above the trenches covered with polysilicon. The exposed SiO.sub.2 is then RIE etched down to the Si.sub.3 N.sub.4, leaving a plug of SiO.sub.2 capped with the etch resistant polysilicon over each trench. These plugs are then removed by mechanical polishing down to the Si.sub.3 N.sub.4, to provide a planarized upper surface of SiO.sub.2 and Si.sub.3 N.sub.4 on the top of the substrate. The invention also is useful in forming planarized surfaces on substrates having trenches filled with conductive material.

REFERENCES:
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patent: 4385975 (1983-05-01), Chu et al.
patent: 4526631 (1985-07-01), Silvestri et al.
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IBM Technical Disclosure Bull., vol. 30, No. 2 (Jul. 1987), pp. 539-540.

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