Active solid-state devices (e.g. – transistors – solid-state diode – With specified dopant
Reexamination Certificate
1999-08-12
2001-07-31
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With specified dopant
C257S288000, C257S328000, C257S335000, C257S404000, C257S408000, C257S605000, C257S616000, C257S655000, C438S162000, C438S303000, C438S305000, C438S520000, C438S525000
Reexamination Certificate
active
06268640
ABSTRACT:
DESCRIPTION
Technical Field
The present invention relates to a method for fabricating a semiconductor device and particularly a MOSFET exhibiting relatively steep lateral doping distribution at source/drain junctions. The present invention is especially advantageous in fabricating CMOS devices. The semiconductor devices of the present invention are fabricated by implanting silicon and/or germanium ions at a tilt angle along with wafer rotation in order to preamorphize the semiconductor substrate. Furthermore, the present invention relates to semiconductor devices obtained by the described fabrication technique.
BACKGROUND OF INVENTION
Field effect transistors (FETs) have become the dominant active device for very large scale integration (VLSI) and ultralarge scale integration (ULSI) applications in view of the high impedance, high density and low power characteristics of integrated circuit FETs.
The most common configuration of FET devices is the MOSFET which typically comprises source and drain regions in a semiconductor substrate at a first surface thereof and a gate region therebetween. The gate includes an insulator on the first substrate surface between the source and drain regions, with a gate electrode or contact on the insulator. A channel is present in the semiconductor substrate beneath the gate electrode, and the channel current is controlled by a voltage at the gate electrode.
More recently, in an effort to reduce the channelling during implantation of source/drain dopants in the vertical or depth direction, the substrate has been preamorphized by implanting ions perpendicular to the substrate in the desired locations. This has resulted in shallower junctions in the vertical direction which in turn improves the short channel characteristics of the device. However, as the junction depth has been scaled down to below for example about 30 nanometers, disadvantages occur due to the reduced junction depth. Such disadvantages include increased source/drain resistance (Rsd) and limitation of dopant activation by silicidation. Any advantages achieved by shallow junction formation are offset by these disadvantages.
It would therefore be desirable to achieve improved short channel characteristics such as threshold voltage (Vt) rolloff along with better scalability of MOSFETs and especially CMOS devices in ULSI circuit design without the prior art problems and disadvantages such as increased source/drain resistance.
SUMMARY OF INVENTION
The present invention makes it possible to achieve improved short channel characteristics including threshold voltage (Vt) rolloff along with better scalability. More particularly, the present invention makes it possible to provide steeper lateral doping profiles near the source/drain junctions of the MOSFET devices.
More particularly, the method of the present invention for fabricating a semiconductor device comprises providing a structure having a semiconductor substrate, gate insulating layer located above selected portions of the semiconductor substrate, gate conductor located above the gate insulating layer. Non-doping ions are implanted into the substrate. The non-doping ions include germanium and/or silicon. The non-doping ions are implanted at a tilt angle &agr; of at least about 10° and at a dosage of at least about 1E14 cm
−2
at an energy of at least about 10 Kev. In addition, the edges of the gate conductor act as a self-aligned mask for implanting the non-doping ions. Dopants are then implanted into the substrate for providing source/drain extensions and/or halo doping.
The present invention also relates to semiconductor devices obtained by the above disclosed process.
The present invention also relates to semiconductor device which comprises a structure having a semiconductor substrate, gate insulating layer located above selected portions of the semiconductor substrate, gate conductor located above the gate insulating layer. The substrate further comprises non-doping ions having been implanted at a tilt angle &agr; of at least about 10° and at a dosage of at least about 1E14 cm
−2
at an energy of at least about 10 Kev. The non-doping ions comprise germanium and/or silicon. The substrate also includes dopants for providing source/drain extensions and/or halo doping.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5223445 (1993-06-01), Fuse
Park Heemyong
Taur Yuan
Wann Hsing-Jen C.
Abate Joseph P.
Connolly Bove Lodge & Hutz
International Business Machines - Corporation
Wojciechowicz Edward
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