Forming self-aligned via holes in thin film interconnection syst

Details Forming self-aligned via holes in thin film interconnection syst Forming self-aligned via holes in thin film interconnection syst

1976-10-28

1978-01-24

Kendall, Ralph S.

Coating processes

Electrical product produced

Condenser or capacitor

427 93, 427 96, 156643, 156652, 156653, 156657, 156662, 204192D, 96 362, H01L 2144

Patent

active

040705013

ABSTRACT:
A method for forming self-aligned via holes which are used to interconnect levels of thin films atop substrates. A first level thin film pattern, typically comprising raised metallic stripes, is formed atop the substrate. A first level dielectric material is then deposited in blanket fashion so that the topology of the insulator conforms to the topology of the pattern. Next, a material such as polymer is deposited which tends to form a planar surface, with a greater thickness of polymer accumulating between the protuberances of the insulator than atop said protuberances. A mask is then applied, exposed and developed at selected regions where via holes are to be formed in the dielectric. A small amount of the polymer is etched, preferably in a plasma, to expose the insulator. Then the latter is etched to form the via holes. Accurately located via holes are formed, even if the mask is misaligned.

REFERENCES:
patent: 3976524 (1976-08-01), Feng

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