Forming resistors for intergrated circuits

Details Forming resistors for intergrated circuits Forming resistors for intergrated circuits

1993-03-25

1994-05-31

Quach, T. N.

Fishing, trapping, and vermin destroying

437 60, 437 78, 437193, 437918, 257536, 448DIG136, H01L 213205, H01L 21283

Patent

active

053169786

ABSTRACT:
A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench. After annealing to diffuse dopant, the wider end contact regions are heavily doped to form contact regions, and the intermediate narrow portion of the trench is doped to a level dependent on the width of the trench, thereby forming a resistive element having a resistivity inversely dependent on the trench width. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes.

REFERENCES:
patent: 4847673 (1989-07-01), Matsukawa
patent: 4910572 (1990-03-01), Kameyama
patent: 5034347 (1991-07-01), Kakihana

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