Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
1998-07-10
2002-12-10
Cuneo, Kamand (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S127000, C438S667000, C438S758000
Reexamination Certificate
active
06492201
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to fabrication of circuit components for use in microelectronics by electrophoretic deposition.
BACKGROUND OF THE INVENTION
Microelectronic assemblies and sub-assemblies such as packaged semiconductor chips, multi-chip modules, and larger circuits utilize many components which include dielectric layers and conductive, typically metallic components on such dielectric layers. For example, as disclosed in commonly assigned U.S. Pat. Nos. 5,148,265; 5,489.749; and 5,518,964, the disclosures of which are hereby incorporated by reference herein, a chip package may include a generally flat, sheet-like dielectric element having metallic conductive features such as terminals, and in some cases, electrically conductive traces extending along a surface of the sheet. These traces may be formed integrally with flexible leads which serve to connect the terminals to contacts on a semiconductor chip. Typically, the sheet-like dielectric element is flexible and is positioned adjacent to the chip. For example, the sheet-like element may overly a surface over the chip and a compliant layer may be provided between the dielectric element and the chip. These elements are sometimes referred to as a “chip carriers” or “interposers.”
Other structures used in microelectronics include single layer and multi-layer circuit panels such as those described, for example, in commonly assigned U.S. Pat. Nos. 5,570,504 and 5,558,928, the disclosures of which are hereby incorporated by reference herein. These circuit panels include one or more layers of a dielectric material with conductive traces extending along the dielectric material. Still other components used in microelectronics include sockets such as those described in commonly assigned U.S. Pat. No. 5,632,631 and commonly assigned PCT International publication WO97/44859, the disclosures of which are also incorporated by reference herein. Conductive features on microelectronic components such as packaged semiconductor chips may be engaged with these sockets to make a temporary or permanent electrical connection.
These aforesaid components most commonly are fabricated by techniques similar to those used to manufacture flexible printed circuits. Such techniques use pre-formed sheets of flexible dielectric materials, most commonly Polyimide and form metallic features on these sheets. For example, metallic features can be formed by selectively depositing metals such as copper on the dielectric sheets, or by laminating the dielectric sheets with sheets of metal and etching the metallic sheets to form the required metallic features. The metallic features in some instances include metallic features extending vertically through a sheet, between its major surfaces, commonly referred to as “vias.” Vias typically are formed by depositing metal into holes extending through the dielectric layer as, for example, by processes such as sputtering, electroless plating and electroplating. As described in some of the foregoing documents, microelectronic connection components such as chip carriers, circuit panels and sockets may incorporate electrically conductive potential plane elements, typically the form of thin, sheet-like metallic layers overlying a dielectric layer or sandwiched between dielectric layers. These potential plane elements typically are connected to a source of a constant potential such as power or ground potential.
As described, for example, in U.S. Pat. No. 5,590,460, the disclosure of which is incorporated by reference herein, layers for use within multi-layer circuit panels have been fabricated by providing a metallic sheet with holes extending through the sheet and depositing a polymeric material such as an epoxy or an acrylic polymer using an electrophoretic deposition process. In the electrophoretic deposition process, the sheet is immersed in a bath containing uncured polymer. An electrical potential is maintained between the sheet and a counterelectrode in contact with the bath. The electrical field causes the uncured polymer to deposit as a thin coating on the sheet. After coating, the sheet is removed from the bath and the still adhering droplets of the bath are removed, as by rinsing the sheet. The uncured polymer is then cured, typically by baking the sheet at an elevated temperature. The resulting continuous dielectric coating covers the major surfaces of the sheet and extends through the holes as well, so as to form hollow dielectric liners extending within the holes of the sheet. As also described in the '460 patent, metallic structures can be formed within the holes of such a layer and can be used to connect adjoining layers of the multi-layer circuit with one another.
Arachtingi, U.S. Pat. No. 4,601,916 discloses a multi-step process in which insulation is provided on opposed surfaces of a metallic sheet; holes are formed in the composite assembly thereby exposing some of the metal within the holes and the metal is then etched back thereby enlarging the holes. Following this etching step, a coating is applied onto the exposed metal surfaces within the holes by an electrophoretic deposition process. Fletcher et al. U.S. Pat. No. 4,714,646 and Japanese patent publication JP01-225197 describe electrophoretic deposition processes forming circuit panel elements. Another process, taught in U.S. Pat. No. 4,783,247 utilizes electrophoretic coating after electrostatic spray coating of metallic cores having holes therein. Still other processes involving electrophoretic deposition of insulators on metal cores of circuit panels are disclosed in Thams, U.S. Pat. No. 4,321,290. Kodani et al., U.S. Pat. No. 5,738,928 discloses a tape automated bonding (“TAB”) tape using a metal core coated with an insulating adhesive material.
Despite considerable interest in the art in using electrophoretic deposition of an insulating layer on a metal conducting layer to make metal core layers, these processes have not been adopted in fabrication of chip carriers heretofore. Certain chip carriers require very fine vias, having diameters below about 100 &mgr;m (0.004 inches) and in some cases 75 &mgr;m (0.003 inches) or less. Processing problems arise when attempts are made to use conventional electrophoretic deposition processes to provide polymeric linings in such small holes in conjunction with continuous polymeric coatings on the surfaces of a metal or other conductive layer. In some instances, the cured polymeric material does not form a continuous polymeric coating over all of the interior surfaces of the holes. Attempts to correct this problem by increasing the time of exposure to the polymeric coating bath or by increasing the electrical potential applied during the coating process can provide a heavier polymeric coating. However, the polymeric coatings typically still suffer from defects within the interior of the holes. If the coating weight is increased to a point where the defects disappear, the coating typically plugs the holes, making it impossible to form conductive structures within the holes.
SUMMARY OF THE INVENTION
One aspect of the present invention provides an improved process for making microelectronic components. The process according to this aspect of the invention includes the step of providing an electrically conductive, typically metallic element such as a sheet or a lead frame having oppositely facing first and second major surfaces and having holes extending through the sheet. A first coating of uncured polymer is deposited by electrophoretic deposition, preferably by immersing the conductive sheet in a liquid bath containing an uncured polymer, contacting the bath with a counterelectrode and applying an electrical potential between the counterelectrode and the conductive sheet to coat the sheet with uncured polymer. After this deposition step, the sheet is removed from the bath and preferably freed from excess polymer by rinsing or otherwise removing loosely adhering polymer and bath solution. The uncured polymer on the sheet is then cured to form a first dielectric coating, typica
Chambliss Alonzo
Cuneo Kamand
Tessera Inc.
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