Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2001-12-28
2004-11-16
Thomas, Tom (Department: 2815)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S084000, C349S132000, C349S139000
Reexamination Certificate
active
06819383
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 2001-29811 filed in Korea on May 29, 2001, the entirety of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to an array substrate having a high storage capacitance and a high aperture ratio, and a fabricating method thereof.
2. Description of the Background Art
A conventional liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecule has a definite orientational order in alignment resulting from its thin and long shape. The alignment direction of the liquid crystal molecule can be controlled by applying an electric field to the liquid crystal molecule. In other words, as the alignment direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Images are displayed since the incident light is refracted to the orientation of the liquid crystal molecules due to the optical anisotropy of the aligned liquid crystal molecules.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images.
FIG. 1
is a schematic cross-sectional view partially showing a liquid crystal panel of an LCD device of the background art. In
FIG. 1
, the liquid crystal panel
20
has an upper substrate
2
, referred as a color filter substrate, and a lower substrate
1
, referred as an array substrate. The upper and lower substrates
2
and
1
are facing and spaced apart from each other and a liquid crystal layer
10
is interposed therebetween. A black matrix
9
that prevents light leakage and a color filter
8
that selectively transmits light are formed on the inner surface of the upper substrate
4
with an overlapped portion. A common electrode
12
that applies a voltage to the liquid crystal layer
10
is formed on the black matrix
9
and the color filter
8
. On the other hand, a pixel electrode
14
that applies a voltage to the liquid crystal layer
10
with the common electrode
12
of the upper substrate
4
is formed at the top of the lower substrate
1
. A thin film transistor (TFT) “T” that is a switch of the voltage applied to the pixel electrode
14
is formed on the lower substrate
2
.
A storage capacitor “Cst” that keeps the voltage applied to the liquid crystal layer
10
for one frame is formed at a pixel region where the pixel electrode
14
is disposed. The types of the storage capacitor “Cst” can be divided into a previous gate type and a common type. In the previous gate type, the pixel electrode and the previous gate line has an overlapping area and this overlapping area is used as the storage capacitor. In the common type, a common line is formed at the pixel region and the storage capacitor is formed between the common line and the pixel electrode. The previous gate type has advantages in aperture ratio and yield, and the common type has advantages in display quality.
Recently, according to the concentration on LCD devices with high definition and high display quality, storage capacitor of a complex type of the previous gate and the common types is being researched.
FIG. 2
is a schematic plan view partially showing an array substrate of an LCD device of the background art having a common type storage capacitor. In
FIG. 2
, a gate line
26
having a gate electrode
22
is formed along a row direction and a common line
24
parallel to the gate line
26
is spaced apart from the gate line
26
. A semiconductor layer
30
is formed on the gate electrode
22
. A source electrode
32
and a drain electrode
34
overlapping the semiconductor layer
30
are spaced apart from each other. A data line
36
connected to the source electrode
32
is formed along a column direction and crossing the gate and common lines
26
and
24
. A pixel electrode
46
is formed at a pixel region defined by the gate and data lines
26
and
36
and a storage electrode
38
is formed in the pixel region.
The storage electrode
38
is made of the same material as the data line
36
and is disposed over the common line
24
with a first area. A TFT includes the gate electrode
22
, the semiconductor layer
30
and the source and drain electrodes
32
and
34
. The pixel electrode
46
is connected to the drain electrode
34
through a first contact hole
42
and connected to the storage electrode
38
through a second contact hole
44
. A gate insulating layer is interposed between the common line and the storage electrode
24
and
38
and a passivation layer is interposed between the storage and the pixel electrodes
38
and
46
. The passivation layer includes first and second contact holes
42
and
44
, and protects the TFT from exterior damage.
In the above-mentioned structure, a storage capacitor “Cst” is formed between the common line
24
and the storage electrode
38
and between the common line
24
and the pixel electrode
46
. The capacitance is defined by the following relationship:
C=&egr;A/d
where C is capacitance, E is permittivity of the interposed dielectric material, A is area of the electrode of the capacitor and d is distance between the electrodes of the capacitor.
Since the gate insulating layer is thinner than the passivation layer, the capacitance between the common line
24
and the storage electrode
38
is larger than that between the common line
24
and the pixel electrode
46
. Therefore, the storage capacitance is increased by adding the storage electrode
38
. However, since the storage electrode
38
is made of opaque metallic material, which is the same material of the data line
36
, an aperture ratio is reduced by adding the opaque storage electrode
38
.
FIGS. 3
to
12
are schematic plan views and their schematic cross-sectional views showing forming process of an array substrate for an LCD device of the background art. In these processes, deposition, photolithography and etching are repeated to form the array substrate.
FIG. 3
is a schematic plan view showing a forming process of an array substrate for an LCD device of the background art.
FIG. 4
is a schematic cross-sectional view showing a forming process of an array substrate for an LCD device of the background art. In FIG.
3
and
FIG. 4
, a gate line
26
having a gate electrode
22
and a common line
24
are formed on a substrate
1
along a row direction. The common line
24
parallel to the gate line
26
is spaced apart from the gate line
26
. A double metallic layer including aluminum (Al) is mainly used as the gate and common lines
26
and
24
.
FIG. 5
is a schematic plan view showing a forming process of an array substrate for an LCD device of the background art.
FIG. 6
is a schematic cross-sectional view showing a forming process of an array substrate for an LCD device of the background art. In FIG.
5
and
FIG. 6
, after a gate insulating layer
28
is formed on the entire surface of the substrate
1
having the gate and common lines
26
and
24
, an active layer
30
a
of amorphous silicon (a-Si) and an ohmic contact layer
30
b
of doped amorphous silicon (doped a-Si) are subsequently formed on the gate insulating layer
28
over the gate electrode
22
to form a semiconductor layer
30
. The ohmic contact layer
30
b
can reduce the contact resistance between the active layer
30
a
and a following metal layer since an ionic doping process increases the carrier mobility of the ohmic contact layer
30
b.
FIG. 7
is a schematic plan view showing a forming process of an array substrate for an LCD device of the background art.
FIG. 8
is a schematic plan cross-sectional view showing a forming process of an array substrate for an LCD device of the background art.
Chae Gee-Sung
Hwang Yong-Sup
Lee Jae-Kyun
LG. Philips LCD Co. Ltd.
Richards N. Drew
Thomas Tom
LandOfFree
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