Forming memory transistors with varying gate oxide thicknesses

Metal working – Method of mechanical manufacture – Assembling or joining

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Details

29576B, 29577C, 29591, 148 15, 148187, H01L 21425

Patent

active

046514066

ABSTRACT:
A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

REFERENCES:
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patent: 4003071 (1977-01-01), Takagi
patent: 4118642 (1978-10-01), Richardson
patent: 4280272 (1981-07-01), Egawa et al.
patent: 4300212 (1981-11-01), Simko
patent: 4373249 (1983-02-01), Kosa et al.
patent: 4471373 (1984-09-01), Shimizu et al.
patent: 4472871 (1984-09-01), Green et al.

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