Fishing – trapping – and vermin destroying
Patent
1986-02-07
1987-08-04
Roy, Upendra
Fishing, trapping, and vermin destroying
357 234, 148DIG77, 437 24, 437 40, H01L 21265, H01L 754
Patent
active
046836373
ABSTRACT:
MOS transistors in which the source and drain contact are isolated from the common substrate are formed by using the gate conductor to mask a high dose high energy implant which creates a thin dielectric region within the body of the common substrate beneath the source and drain regions, but not beneath the channel region. For single crystal silicon substrates, oxygen and nitrogen are the preferred ions for use in forming the buried dielectric region. The conductive gate must be sufficiently thick so as to preclude the implanted oxygen or nitrogen ions from reaching the underlying gate dielectric or the portion of and channel region of the device will be substantially free the substrate beneath the gate. This ensures that the gate and channel region of the device will be substantially free of the implant damage which otherwise occurs during formation of the buried dielectric regions. Dielectric isolation walls are conveniently provided laterally exterior to the source-drain regions. The source-drain and gate regions are self-aligned to each other. Typical oxygen implant doses to form the buried dielectric layer are 1.7.-2.2.times.10.sup.18 ions/cm.sup.2 at an energy of about 150 KeV.
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Burnham Marie E.
Varker Charles J.
Wilson Syd R.
Handy Robert M.
Motorola Inc.
Roy Upendra
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