Forming an integrated circuit

Details Forming an integrated circuit Forming an integrated circuit

1981-06-05

1983-08-02

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29577C, 148175, 148187, H01L 21265

Patent

active

043958125

ABSTRACT:
A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and gate in the P-type base region of what would otherwise have been an NPN transistor. Both an NPN type BIFET and an PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.

REFERENCES:
patent: 4049476 (1977-09-01), Horie
patent: 4066917 (1978-01-01), Compton et al.
patent: 4110126 (1978-08-01), Bergeron et al.
patent: 4143392 (1979-03-01), Mylroie
patent: 4233615 (1980-11-01), Takemoto et al.
patent: 4314267 (1982-02-01), Bergeron et al.

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