Forming a vertical PNP transistor

Fishing – trapping – and vermin destroying

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437 74, 257 37, H01L 21265, H01L 2970

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053025342

ABSTRACT:
A transistor (10) is formed by utilizing an isolated well (18) within a thin epitaxial layer (14). A base mask (22) that has a base opening (23) is applied to expose a portion of the isolated well (18). A low resistance collector enhancement (24) is formed within the well (18) by doping a portion of the well (18) through the base opening (23). A base region (26) is formed overlying the collector enhancement (24) by doping the well (18) through the base opening (23). Forming the collector enhancement (24) through the base opening (23), facilitates providing the collector enhancement (24) with a small area thereby minimizing the transistor's (10) parasitic collector capacitance value, collector resistance, and transit time.

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D. de Lang et al., "Integration of Vertical PNP Transistors in . . . ", IEEE Bipolar Circuits and Tech. Meeting, pp. 190-193, (1989).
Pong-Fei Lu et al, "Stimulations of Collector Resistance of PNP . . . ", Solid State Electronics, vol. 32, No. 8, pp. 675-678, (1989).
K. Higashitani et al. "A Novel CBi-CMOS Tech. by DIIP . . . ", IE.sup.3 Symposium on VISI Tech., pp. 77-78, (1990).

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