Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2007-01-02
2007-01-02
Brewster, William M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S730000, C257SE23167
Reexamination Certificate
active
10662636
ABSTRACT:
A method is provided for processing a semiconductor topography such that its upper surface is substantially planar, particularly including a region adjacent to an outer edge of a semiconductor topography. The method may include preferentially removing a portion of an upper layer of the topography in a region adjacent to an outer edge of the semiconductor topography. The region may extend greater than approximately 3 mm inward from the outer edge of the semiconductor topography. The method may also include polishing the semiconductor topography such that the upper surface of the semiconductor topography is substantially planar. Therefore, although a rate of polishing adjacent to an outer edge of the semiconductor topography may be slower than a rate of polishing adjacent to a center of the semiconductor topography, a thickness variation of the polished upper layer across the entirety of the semiconductor topography may be less than approximately 500 angstroms.
REFERENCES:
patent: 4193226 (1980-03-01), Gill, Jr. et al.
patent: 4811522 (1989-03-01), Gill, Jr.
patent: 5421769 (1995-06-01), Schultz et al.
patent: 5783482 (1998-07-01), Lee et al.
patent: 5918139 (1999-06-01), Mitani et al.
patent: 6010964 (2000-01-01), Glass
patent: 6020639 (2000-02-01), Ulrich et al.
patent: 6091130 (2000-07-01), Oyamatsu et al.
patent: 6376363 (2002-04-01), Iguchi
patent: 6472291 (2002-10-01), Page et al.
Malkoe et al., “Effect of Retaining Ring System on the Polishing of 300 mm Oxide Wafers,” Mar. 2001, pp. 519-522.
Wolf,Silicon Processing for the VLSI Era, vol. 2: Process Integration, © 1990 by Lattice Press, pp. 238, 239.
Buchanan Matthew D.
Held Ruediger
Jayatilaka Venuka K.
Brewster William M.
Cypress Semiconductor Corp.
Daffer Kevin L.
Daffer McDaniel LLP
Lettang Mollie E.
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