Forming a device dielectric on a deposited semiconductor having

Details Forming a device dielectric on a deposited semiconductor having Forming a device dielectric on a deposited semiconductor having

1993-06-16

1994-03-29

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 43, 437112, 437141, 437191, 437233, 156613, 156614, H01L 2120

Patent

active

052984362

ABSTRACT:
A high quality dielectric layer, typically silicon dioxide, is formed on a multi-layer deposited semiconductor structure, typically polysilicon or amorphous silicon. The multi-layer structure is formed by varying the silicon deposition rate so as to obtain a low stress deposited silicon structure. The low stress allows for a higher quality dielectric to be formed on the exposed top surface. One application is for thin film transistor gate oxides. Other applications included capacitor dielectrics and the tunnel oxide on the floating gate of EEPROMs.

REFERENCES:
patent: 4631804 (1986-12-01), Roy
patent: 4742020 (1988-05-01), Roy
patent: 4814291 (1989-03-01), Kim et al.
patent: 4992391 (1991-02-01), Wang
Abstract No. 257, S. P. Tay, J. P. Ellul, M. I. H. King, J. J. White, "Thin Gate and Poly Oxides by High-Pressure Silicon Oxidation", (1985) Oct., No. 2 Pennington, N.J., USA, pp. 386, 387.
Abstract No. 258, J. P. Ellul, S. P. Tay, J. J. White, M. I. H. King, "Nitsinitride VLSI Dielectrics", (1985) Oct., No. 2, Pennington, N.J., USA, pp. 388, 389.

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