Forming a chip package having a no-flow underfill

Details Forming a chip package having a no-flow underfill Forming a chip package having a no-flow underfill

2006-08-01

2006-08-01

Andujar, Leonardo (Department: 2826)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C438S108000, C257S783000, C257S778000

Reexamination Certificate

active

07084011

ABSTRACT:
A method of forming an underfilled chip package is provided. No-flow underfill material is deposited over a surface of a package substrate to form an underfill region. A die having a plurality of solder bumps is placed at an angle relative to the package substrate such that solder bumps adjacent a first side of the die contact the surface of the package substrate within the underfill region while solder bumps adjacent a second side of the die are generally located at a distance away from the surface of the package substrate. The second side of the die is moved toward the surface of the package substrate until the solder bumps adjacent the second side of the die contact the surface such that the underfill material is forced into the area between the plurality of bumps.

REFERENCES:
patent: 6069024 (2000-05-01), Murakami
patent: 6404062 (2002-06-01), Taniguchi et al.
patent: 6576495 (2003-06-01), Jiang et al.
patent: 2002/0043711 (2002-04-01), Akram et al.

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