Formatter for high speed test system

Details Formatter for high speed test system Formatter for high speed test system

1984-05-17

1987-01-06

Atkinson, Charles E.

Excavating

371 20, G01R 3128

Patent

active

046352562

ABSTRACT:
A formatting circuit for a high speed integrated circuit test system controls the application of timed data pulses to the input terminals of the device being tested, generates strobe signals to control comparators connected to the output terminals of the device being tested, and provides circuitry to decode error signals received from the device being tested. The formatting circuit routes all critical signal paths to the device under test over separate signal lines, thereby allowing compensation for the different propagation delay of each signal path. The input transitions and output strobe signals for the device being tested are not fixed in time with respect to the system clock, but are referenced to it. This enables drive data cycles and compare data cycles to be less dependent on the system clock, and permits them to overlap and cross test period boundaries. Multiple test vectors for a given test period are permitted and error correlator decodes error signals produced by incorrect output signals from the device under test. The error correlator decodes these error signals and logs them in a memory location corresponding to the proper test vector.

REFERENCES:
patent: 4488297 (1984-12-01), Vaid
patent: 4497056 (1985-01-01), Sugamori
patent: 4523312 (1985-06-01), Takeuchi

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