Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-03-16
2003-03-25
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S705000, C438S156000, C438S207000, C438S481000
Reexamination Certificate
active
06537920
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
FIELD OF THE INVENTION
The present specification relates generally to the field of integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present specification relates to a method of reducing transistor size and spacing by producing transistors in integrated circuits using block copolymer lithography.
BACKGROUND OF THE INVENTION
This invention relates generally to manufacturing processes for fabricating semiconductor integrated devices. More particularly, it relates to an improved method of forming transistors in integrated circuits that are smaller than what is achievable by conventional lithographic technology.
As is generally known in the semiconductor industries, there is a continuing trend of manufacturing integrated circuits with higher and higher device densities on a smaller chip area. This desire for large scale integration has led to a continued shrinking of the circuit dimensions and features of the devices so as to reduce manufacturing costs and to improve circuit functionality. Reducing the size and spacing of integrated circuit devices is a function of the method used to fabricate those devices.
Producing integrated circuit devices requires the use of lithography, in which patterns of device features are transferred to a resist layer on a semiconductor substrate and portions of the resist layer is selectively removed according to the pattern to produce apertures in the resist layer. Using known etching techniques, the material underlying the resist layer may be selectively etched to produce apertures in the underlying material, since only the areas underlying the apertures will be etched, while the area under the remaining resist layer will be unaffected by the etchant. Following this selective etching, material may be introduced into the apertures in the underlying material to create devices on the integrated circuit.
Several lithographic methods may be used to pattern devices in integrated circuits. Photolithography involves the deposition of a light-sensitive polymer resist onto a material surface. The polymer resist layer is then selectively exposed to light through a mask and developed to create a pattern of holes in the resist. The material underlying the patterned holes may then be etched away to create devices. Despite success using this method, there are negative aspects as well. For example, it is costly and time-consuming to produce light masks which allow selective patterning of the polymer resist. Further, diffraction of the exposing light around the edges of the mask places a limit on the resolution of photolithography such that devices below a certain size and spacing may not reliably be produced.
Periodic patterning using electron beam lithography has also been used in the integrated circuit industry. No masks are required, as the pattern is transferred by using a finely focused beam of electrons to “draw” a pattern on the wafer surface. Patterning of devices is limited, however, in that production of devices having feature sizes below 30 nm is difficult to achieve with commercial electron beam systems. Further, minimum spacing between adjacent devices using electron beam technology is at best 50 nm, and generally not much below 100 nm. Finally, each device must be created individually, such that patterning of many millions of devices on a single integrated circuit is time consuming and results in lower throughput than with photolithography. Ion beam and x-ray lithography techniques suffer from the same defects as electron beam lithography.
The shortcomings of current lithographic methods result in the formation of transistors which are not fully depleted, as full depletion of transistors requires device dimensions smaller than 50 nm.
Block copolymers consist of at least two chemically different homopolymer chain types (also referred to as “segments” or “blocks”) connected by covalent bonds. In bulk, similar homopolymer chains spontaneously align to form nanometer-sized domains of like composition that exhibit ordered morphologies. For example, one can create a copolymer film having spheres of polybutadiene in a polystyrene matrix. Increasing or decreasing the number of polymer units in the respective homopolymer chains will alter the homopolymer chain length and molecular weight, and will result in varied bulk morphologies. Periodic arrangements of various shapes, including lamellae, cylinders, or spheres, may be created in this manner.
The chemical difference between the homopolymer chains may be exploited to aid in processing integrated circuit features with very small dimensions. Selectively removing one type of polymer chain from the polymer matrix (e.g. removing the polybudatiene spheres from the polystyrene matrix in the above example) results in a patterned array of voids in the bulk copolymer that could be used as a patterned resist layer, much the same as with other lithographic techniques. One advantage of using masks of patterned copolymer is that the size of devices may be reduced and periodicity of device features may be increased.
Accordingly, there is a need to reduce integrated circuit device dimensions below 50 nm. Further, there is a need to produce integrated circuits having increased device packing density. Even further, there is a need to concurrently produce many devices having increased packing density and reduced device dimensions to increase fabrication throughput.
SUMMARY OF THE INVENTION
According to one exemplary embodiment, a method of forming a vertical transistor in an integrated circuit using block copolymer lithography includes providing a dielectric layer over a semiconductor. The method further includes depositing a layer of copolymer over the dielectric layer. The copolymer has a first polymer type and a second polymer type. The method further includes removing portions of the first polymer type from the copolymer layer to form a void in the copolymer layer and removing a portion of the dielectric layer underlying the void to form an aperture in the dielectric layer. The method further includes providing a semiconductor material in the aperture.
According to another exemplary embodiment, a method of producing an integrated circuit includes forming an oxide layer on a semiconductor substrate and forming a nitride layer over the oxide layer. The method further includes depositing a layer of diblock copolymer over the nitride layer. The diblock copolymer has a first polymer type and a second polymer type. The method further includes removing a portion of the first polymer type from the copolymer layer to form hollow regions in the diblock copolymer layer and removing a portion of the nitride layer underlying the hollow regions to form apertures in the nitride layer. The method further includes removing a portion of the oxide layer underlying the apertures in the nitride layer to form apertures in the oxide layer and forming pillars of semiconductor material in the apertures.
According to another exemplary embodiment, an integrated circuit having at least one million transistors is fabricated by providing an oxide layer on a silicon substrate and providing a nitride layer over the oxide layer. The process further includes providing a copolymer layer over the nitride layer. The copolymer layer has a first polymer type and a second polymer type. The first polymer type segregates to form regions of the first polymer type in a matrix of the second polymer type. The first copolymer type has carbon-carbon double bonds in the polymer backbone. The process further includes exposing the copolymer layer to ozone to create fragments of the first polymer type and removing the fragments of the first polymer type to create voids in the matrix of second polymer type and removing portions of the silicon nitride layer underlying the voids to form apertures in the nitride layer. The process further includes removing a portion of the oxide layer underlying th
Advanced Micro Devices , Inc.
Foley & Lardner
Rocchegiani Renzo N.
Smith Matthew
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