Formation of sub-groundrule features

Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means

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438692, 438694, 438700, 438702, 438759, 438778, H01L 21302, H01L 2131

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060514973

ABSTRACT:
A method of forming very small diameter metal lines in a dielectric layer 12 comprising forming an opening in the dielectric layer using photolithographic techniques, filling the opening with an insulating material 16 and planarizing the dielectric layer using chemical metal polishing techniques, which are continued so as to form small trenches 17 in the dielectric material on either side of the insulating material, filling in the trenches with metal and planarizing the metal layer using chemical metal polishing.

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patent: 5661053 (1997-08-01), Yuan
European Patent Office--Abstract of Japan, Pub. No. 10107161, dated Apr. 24, 1998.
European Patent Office--Abstract of Japan, Pub. No. 09148430, dated Jun. 6, 1997.

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