Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Patent
1999-02-05
2000-11-21
Picardat, Kevin M.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
438422, 257522, H01L 2176
Patent
active
061502324
ABSTRACT:
A method for creating low intra-level dielectric interface between conducting lines using conventional deposition and etching processes. A layer of conducting lines is formed interspersed with dielectric material. A dummy, high-density pattern of low k dielectric material is created on top of this layer. The dielectric material between the metal lines is removed. The dummy high-density pattern is interconnected, deposited on top of this interconnected layer is a low k dielectric to form an inter layer dielectric.
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Cha Cher Liang
Chan Lap
Ong Kok Keng
Tee Kheng Chok
Chartered Semiconductor Manufacturing Ltd.
Picardat Kevin M.
Pike Rosemary L. S.
Saile George O.
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