Formation of integrated circuit electrodes

Details Formation of integrated circuit electrodes Formation of integrated circuit electrodes

1989-11-30

1991-10-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437 57, 437 83, 437 90, 437 41, H01L 21283

Patent

active

050574558

ABSTRACT:
In the fabrication of electrodes for transistors in the BiCMOS integrated circuit, vertical windows etched in a relatively thick TEOS (or other suitable dielectric) layer, located on a relatively thin polysilicon layer, in turn located on relatively tin oxide layer areas and on relatively thick oxide layer areas, are used to define areas where polysilicon electrode material is to remain. Polysilicon is deposited in the windows in the relatively thick insulating layer, to form the basis for the desired electrode in each window. The relatively thin polysilicon layer (or, alternatively an .alpha.-amorphous silicon layer) is thereafter used as an etch stop during the subsequent removal of the relatively thick dielectric layer. Thereafter both MOS and bipolar transistors can be fabricated using the windows to define the extents of the gate regions of the MOS transistors and the extents of the emitter regions of the bipolar transistors. In addition, both the source and drain electrodes of the MOS transistors and the base electrodes of the bipolar transistors can then be simultaneously formed in a self-aligned manner without the need for etching into the underlying semiconductor substrate in which the integrated circuit is being formed.

REFERENCES:
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patent: 4824796 (1989-04-01), Chiu et al.
Ghandhi, S. K., VLSI Fabrication Principles, John Wiley & Sons, 1983, pp. 420-435, 492-495.
Pfiester, J. R., et al, "A Self-Aligned LDD/Channel . . . " IEEE IEDM: Device Technology Subcommittee, 1989, 3 pages.

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