Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2008-07-15
2008-07-15
Tsai, H. Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S522000, C257SE27109
Reexamination Certificate
active
11408100
ABSTRACT:
A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.
REFERENCES:
patent: 4104086 (1978-08-01), Bondur et al.
patent: 5098856 (1992-03-01), Beyer et al.
patent: 5411913 (1995-05-01), Bashir et al.
patent: 6165890 (2000-12-01), Kohl et al.
patent: 6180995 (2001-01-01), Hebert
patent: 6268637 (2001-07-01), Gardner et al.
patent: 6287979 (2001-09-01), Zhou et al.
patent: 6307247 (2001-10-01), Davies
patent: 6448174 (2002-09-01), Ramm
patent: 6645832 (2003-11-01), Kim et al.
patent: 7015116 (2006-03-01), Lo et al.
patent: 2002/0182819 (2002-12-01), Schrems et al.
patent: 2003/0098493 (2003-05-01), Marty et al.
patent: 2003/0183943 (2003-10-01), Swan et al.
patent: 2003/0186486 (2003-10-01), Swan et al.
patent: 2004/0058549 (2004-03-01), Ho et al.
patent: 2004/0147093 (2004-07-01), Marty et al.
patent: 0 519 852 (1992-12-01), None
patent: 0 519 852 (1992-12-01), None
patent: 1 261 021 (2002-11-01), None
patent: 11 243142 (1999-09-01), None
patent: 2000 183149 (2000-06-01), None
patent: 2001 326325 (2001-11-01), None
patent: WO 01/26137 (2001-04-01), None
European Search Report for related European Application No. 05447015.8-2203, dated Mar. 2, 2006.
Washio, et al., A 50-GHz Static Frequency Divider and 40-Gb/s MUX/DEMUX Using Self-Algined Selective-Epitaxial-Growth SiGe HBTs with 9-pcs ECL, IEE Transactions on Electronic devices, vol. 48, 2001.
Patent Abstracts of Japan, vol. 1999, No. 14; JP 11 243142 A Sep. 7, 1999, (Abstract only).
Patent Abstracts of Japan, vol. 2000, No. 9; JP 2000 183149 A Jun. 30, 2000, (Abstract only).
Gutmann R. J. et al.: “Three-dimensional (3D) ICs: A technology platform for integrated systems and opportunities for new polymeric adhesives” First International IEEE Conference on Polymers and Adhesives in Microelectronics and Photonics. Incorporating Poly, PEP & Electronics. Proceedings, Oct. 21, 2001, pp. 173-180, XP002368204.
Unpublished U.S. Appl. No. 11/305,421, filed Dec. 16, 2005 to Vanhaelemeersch, et al.
Interuniversitair Microelektronica Centrum (IMEC vzw)
Knobbe Martens Olson & Bear LLP
Tsai H. Jey
LandOfFree
Formation of deep trench airgaps and related applications does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Formation of deep trench airgaps and related applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Formation of deep trench airgaps and related applications will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3916812