Formation of buried diffusion devices

Fishing – trapping – and vermin destroying

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357 68, 357 34, 148DIG147, 156643, 156653, 437 67, 437 72, H01L 2100

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047110171

ABSTRACT:
A low collector parasitic resistance in bipolar transistors may be achieved without the use of an epitaxial layer or a high energy implant. Essentially, the invention employs the use of trenches in an N.sup.- layer overlying a P.sup.- substrate to surround the transistor, forming an N.sup.+ region in the walls defining the trench and below the surface, extending the trench into the P.sup.- substrate, implanting the bottom of the trench with a P-type dopant and refilling the trench with insulating material.
The process of the invention permits fabrication of complex bipolar integrated circuits having a very high performance, and is particularly adaptable to very small geometry devices of 1 .mu.m and lower.

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patent: 4466180 (1984-08-01), Soclof
patent: 4520552 (1985-06-01), Arnould et al.
patent: 4528047 (1985-07-01), Beyer et al.
patent: 4631803 (1986-12-01), Hunter et al.

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